X's during simulation

Discussion in 'Cadence' started by ricky, Oct 11, 2004.

  1. ricky

    ricky Guest

    Hi,

    I have a problem, I got X's in the simulation results. Could anybody explain
    me the ways to trace the origin of X's. I am using NCsim.
    Your help is very much appreciated.

    Thanks in advance.
     
    ricky, Oct 11, 2004
    #1
  2. Check the output of your rams; it is usually 'X' after reset. Search
    the netlist from the point where you have the 'X' and work backwards
    looking at all inputs.


    Kai
     
    Kai Harrekilde-Petersen, Oct 11, 2004
    #2
  3. Hi ricky,
    The general procedure is to find wether things after reset happen as
    it is expected to. for example let's assume you are simulating a processor.
    1. first you have to check wether you've the processor reset properly
    2. then wether the processor starts fetching from the start address
    3. if yes wether is it getting proper instruction
    4. if yes wether it is behaving as it is supposed to ...

    generally see wether some important signals like reset, test/functional
    mode select input .... pins are in proper values...

    If the system goes to 'x' after some time of the startup, then look at
    the first error message in your transcript and start working from there...

    another cause may be your PLL. It should be fed proper clock to get back
    the multiplied clock. Also its inputs should be in proper values...
    Check your crystal oscillator too...

    HTH

    Narendran Kumaragruru Nathan
    TooMuch Semiconductor Solutions
    www.toomuchsemi.com
    A Bangalore based startup specialising on services in EDA &
    Verification.
     
    Narendran Kumaraguru Nathan, Oct 12, 2004
    #3
  4. ricky

    raman Guest

    Hi Ricky,

    There is no need to get annoyed with X's showing up in the simulation,
    since it is the "model" that is responsible, rather than the simulator
    (except the few cases mentioned below in the paragraph).
    An "X" is just a way, by means of which a model communicates its behavior
    in the same way it does with 0's and 1's. In general X's are used to
    describe unknown state of the circuit(which could either be a "0" or "1"
    in a digital logic) at that particular point in time. The "X" originates
    most of the time from the model to reflect the intended behavior of the
    circuit. An "X" could also be generated by the simulator as the result of
    a system task that captures a timing violation. It is also possible that
    you are having multiple drivers on the same net without a resolution function
    defined, which could make the simulator generate an "X" instead.

    Tracing the origin of "X" is similar to tracing an intended output
    as a result of the relevant inputs, except that in this case, the intended
    output is an "X". As long as you know basic circuit theory and "some"
    understanding of how the HDL's work, it should not be a difficult task.
    It might also benefit, if you could understand the model a bit to verify
    how the intended behavior is implemented(and also to validate the correctness
    of the model).

    Regards
    Raman
     
    raman, Oct 12, 2004
    #4
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.