why cannot I pass the "Cell Placement" in SE? The site utilization is = 140.2 is too high! Impossibl

Discussion in 'Cadence' started by walala, Sep 2, 2003.

  1. walala

    walala Guest

    I set the row utilization in "initialization floorplan" to be 70%,

    Can anybody tell me why I get error message in after "Cell Placement"
    to be "too high row utilization -- 140%"?

    thanks a lot,

    -Walalla

    --------------------------------------------------------------------------
    15:58:56 * PLACE : The site utilization is = 140.2 is too high!
    ** SE-USER-61 ERROR **
    15:58:56 * PLACE : * Impossible to place without overlaps!

    --------------------------------------------------------------------------


    15:58:47 * PLACE :
    15:58:47 * PLACE : Begin LEF/DEF in ...
    15:58:47 * PLACE : Reading "dbs/fir_srg.opt.lef" ...
    15:58:51 * PLACE : Reading "dbs/fir_srg.opt.def" ...
    ** SE-USER-60 WARNING **
    15:58:53 * PLACE : design has no clock net
    15:58:53 * PLACE : A total of 1 warning.
    15:58:53 * PLACE : Read in 11 layers, 4 routing layers, 0 overlap
    layer
    15:58:53 * PLACE : Read in 132 macros, 18 used
    15:58:53 * PLACE : Read in 414 components
    15:58:53 * PLACE : 414 core components: 414 unplaced, 0 placed, 0
    fixed
    15:58:53 * PLACE : Read in 17 physical pins
    15:58:53 * PLACE : 17 physical pins: 0 unplaced, 17 placed, 0 fixed
    15:58:53 * PLACE : Read in 2 logical pins
    15:58:53 * PLACE : Read in 429 nets
    15:58:53 * PLACE : Read in 3 special nets
    15:58:53 * PLACE : Read in 2056 terminals
    15:58:53 * PLACE : End LEF/DEF in: cpu: 0:00:04, real: 0:00:07, peak:
    16.70 megs.
    15:58:53 * PLACE :
    15:58:53 * PLACE : Begin buildData ...
    15:58:53 * PLACE : SiliconEnsemble(TM) placement mode
    15:58:53 * PLACE : design name = fir_srg
    15:58:53 * PLACE : number of instance = 414
    15:58:53 * PLACE : number of placeable core instance = 414
    15:58:53 * PLACE : number of fixed core instance = 0
    15:58:53 * PLACE : number of placeable block instance = 0
    15:58:53 * PLACE : number of fixed block instance = 0
    15:58:53 * PLACE : number of placeable IO instance = 0
    15:58:53 * PLACE : number of fixed IO instance = 0
    15:58:53 * PLACE : number of pin = 17
    15:58:53 * PLACE : number of placeable spare cell = 0
    15:58:53 * PLACE : number of special net = 3
    15:58:54 * PLACE : number of net = 429
    15:58:54 * PLACE : number of site = 1
    15:58:54 * PLACE : number of core site = 1
    15:58:54 * PLACE : number of pad site = 0
    15:58:54 * PLACE : core box = ((-151.50 -126.00)(153.00 130.00))
    15:58:54 * PLACE : row orientation = horizontal, row height = 1
    15:58:54 * PLACE : number of core site per core row = 203
    15:58:54 * PLACE : number of core row = 19
    15:58:54 * PLACE :
    15:58:54 * PLACE : number of routing layer = 4
    15:58:54 * PLACE : layer 1 = Metal1 (metal1), average pitch = 1.5, dir
    = horizontal
    15:58:54 * PLACE : tracks in core = 171, freeTrackPct.1 = 10%
    15:58:54 * PLACE : average blockage for core inst = 100%
    15:58:55 * PLACE : LLC.Ignore.Layer.1 = true
    15:58:55 * PLACE : layer 2 = Metal2 (metal2), average pitch = 1.5, dir
    = vertical
    15:58:55 * PLACE : tracks in core = 203, freeTrackPct.2 = 70%
    15:58:55 * PLACE : average blockage for core inst = 10%
    15:58:55 * PLACE : LLC.Ignore.Layer.2 = true
    15:58:55 * PLACE : layer 3 = Metal3 (metal3), average pitch = 1.5, dir
    = horizontal
    15:58:55 * PLACE : tracks in core = 171, freeTrackPct.3 = 100%
    15:58:55 * PLACE : average blockage for core inst = 0%
    15:58:55 * PLACE : LLC.Ignore.Layer.3 = true
    15:58:55 * PLACE : layer 4 = Metal4 (metal4), average pitch = 3.0, dir
    = vertical
    15:58:55 * PLACE : tracks in core = 102, freeTrackPct.4 = 60%
    15:58:55 * PLACE : average blockage for core inst = 0%
    15:58:55 * PLACE : LLC.Ignore.Layer.4 = true
    15:58:55 * PLACE :
    15:58:55 * PLACE : total site size = 3857 (100.00%)
    15:58:55 * PLACE : total core inst size = 5406 (140.16%)
    qty=414
    15:58:55 * PLACE : average row utilization = 140.16%
    15:58:55 * PLACE :
    15:58:55 * PLACE : num inst of height 2 = 414 5406 sites
    (100.0% of inst sites)
    15:58:56 * PLACE : min-max inst length = 3-22
    15:58:56 * PLACE : average inst length = 6.53, standard deviation =
    5.53
    15:58:56 * PLACE :
    15:58:56 * PLACE : The site utilization is = 140.2 is too high!
    ** SE-USER-61 ERROR **
    15:58:56 * PLACE : * Impossible to place without overlaps!
    15:58:56 * PLACE : PLACE FAILS
    Place interface : Elapsed date = 0
    Place interface : Elapsed time = 0:00:20
    Place interface : CPU time used = 0:00:05
     
    walala, Sep 2, 2003
    #1
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  2. walala

    Muzaffer Kal Guest

    Look at your floor plan output to see what the core size, site size
    and utilization are at that point. It is possible that you're using
    the Floorplan command in SE incorrectly.

    Muzaffer Kal

    http://www.dspia.com
    ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations
     
    Muzaffer Kal, Sep 3, 2003
    #2
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