What's the common utilization ratio in Silicon Ensemble P&R in practice for a mid-large design?

Dear all,

I am doing a design with Leda system library, 0.25 tsmc process, with 18000+
cells and 19000+ nets. I have been doing P&R using SE for one month... tried
a number of variations... It turns out if the row utilization is >80%, the
"Place cell" will fail with message "unable to place without overlap!"... if
the utilization is >50%, the over capacity in Place cells will be > 30% and
then "Wroute" will fail with message "too many Geometry violations"...after
several days running...

So far the only wroutable solution I've got is with a utilization ratio of
26%... the wroute only needs 28 minutes to run in this case, without any
violation. But since I've added filler cells before wroute, the filler cells
were a lot and the total number of cells/components was 700000+,(since the
total area is too large) whihc led to very hard time and long running for
the later icca, icfb layout, extract, DRC, LVS, extract netlist, etc...

Can anybody tell me if the utilization 26% is too low, and abnormal? What
can I do to fine tune it up? Is there any hidden tricks I might neglected
even I have read manuals, doing trial and errors for one month?

thanks a lot,

Walala

 

Hi,

I'm not familiar with the TSMC library you mention - but 26% utilisation
would be "ridiculously" low for any of the digital designs I've been
working
on. For an all-digital block, I'm used to seeing utilisation figures of
over
90%.

Are you trying to do anything out of the ordinary, like odd form factor
of
your design (2:1 form factor needs more area than a square design) or
power
stripes instead of rings (power stripes use up row area !) ?
Are you using the right cell row configuration for these cells - don't
try
to use flipped and abutted rows with cells that aren't intended for it.

I would say your best bet to get beyond this is to study the library
documentation for any place & route related info. Also check if the
library
provides setup files (se.ini file, or even a qplace and wroute config
file)
to tune SE for this library.

Best regards,

Han.

 

Dear Han Speek,

Your comments and suggestions were of the greatest help to me. I was doing
this work blindly in the whole past month. P&R over and over and again and
again, doing trial and error... After getting your suggestions, I thought
my procedure again and again. And did a few experiments. After all, it
turned out that simply changing the "flip" and "abut" combinations matters a
lot, not to say the other factors you've mentioned about.

Now I am doing experiments on different combinations, and found out that
with 40% utilization, and "flip" + "abut" + row spacing = 1 track, I can
remove all violations! How happy I was... for the first time in this one
month, I saw violations removed for about 40% utilizations. I have seen the
violations dropped from 100000+ down to 0 magically! Thank you so much and
now I think I can do more! At the beginning of this month I was so
inexperienced that I asked too much for the SE and it got a lot of 100000+
violations after several days running...

Yet just one small problem, I still have 1 open remained after CONNECT RING
command, before I do WROUTE. Is there any search and repair kind of function
for CONNECT RING? What can I do to eliminate this only remaining OPEN? Is it
helpful to put a stripe?(Currently I am not doing any stripe, after seeing
your suggestions). Is there a incremental/search-repair "PLACE", maybe redo
"PLACE" will help?

I am a little sure that if I put "filler cells", maybe this 1 open will
gone. But I don't want to put "filler cells" because since the circuit is
large, there are a lot filler cells to add, and the post processing, for
example the layout extraction and LVS will be untolerably long... Since I am
not really doing a chip, all I need is just post-layout-extraction
transistor level simulation, so I can leave out filler cell, ...

Thank you SO MUCH for your help and now I am a lot confident about myself!
Originally I really think I am an idiot...

Best,

-Walala

 

Hi again,

What I've found (with some help of the Cadence support guys) is that
adding
the line:

set v sroute.followpins.simplevia true ;

to the se.ini file will often help solving strange bugs in the CONNECT
RING
step. You could give that one a try - see if it helps.

Regarding the placement, there IS a placement optimization in the menus
in the later SE versions (I'm using 5.4.123 myself), and it seems to
work too

I'm not so sure you can leave out the filler cells, even if it's only
for
extraction. In many technologies, the filler cells also connect the
wells
so that in a row there is one continuous Nwell and one continuous Pwell.
Rows with segmented wells could give quite different results (unless you
use
Diva macro extract). Also, depending on how the supplies in the cells
are
organized, the filler cells may be needed to (by abutment) get correct
power
and ground track widths, rather than have the router connect them.

Look in your library for the largest filler cell available, and start
placing these. Then the next-largest, then one smaller etc. That way you
will get the minimum number of filler cells.
You could write a macro to do this, which would look sort of like:

SROUTE ADDCELL MODEL filler17 PREFIX fill NO FN SO FS SPIN gnd! NET gnd!
SPIN vdd! NET vdd! PREADDEDCELLSFIXED AREA (-750000 -350000) (750000
350000) ;
SROUTE ADDCELL MODEL filler13 PREFIX fill NO FN SO FS SPIN gnd! NET gnd!
SPIN vdd! NET vdd! PREADDEDCELLSFIXED AREA (-750000 -350000) (750000
350000) ;
SROUTE ADDCELL MODEL filler11 PREFIX fill NO FN SO FS SPIN gnd! NET gnd!
SPIN vdd! NET vdd! PREADDEDCELLSFIXED AREA (-750000 -350000) (750000
350000) ;
SROUTE ADDCELL MODEL filler7 PREFIX fill NO FN SO FS SPIN gnd! NET gnd!
SPIN vdd! NET vdd! PREADDEDCELLSFIXED AREA (-750000 -350000) (750000
350000) ;
(do it manually once, and then cut and paste the proper commands from
the se.jnl file)

Then you can execute the macro by typing "exec filler.mac ;" (don't
forget the semicolon !) in the SE command line.

Glad to have been able to help,

Han.

 

One hint: check if the routing grid is defined properly.
The easiest way: zoom close to a few cells and check if the pins of the
cells contain well centered grid line crossings - this should be the
case if the grid is well set and the library is properly defined.

Regards,

Robert

 

We have been using our in-house library for 0.5micron 3M process. Even with
that library and adding power rings and stripes, we were able to get a row
utilization of more than 40%(for a design of 2 x 1.5 mm). With a 6M process,
you should be able to get more row utilization. Check the documentation of
the library.

Prasanna.