what must be associated in verilog file with LEF when imported in the SOC ENCOUNTER?

Discussion in 'Cadence' started by Echo, Feb 18, 2004.

  1. Echo

    Echo Guest

    Hello!
    I import the verilog file netlist and the LEF of abstract generator
    into the SOC ENCOUNTER,but after floorplan,there are some triangle
    pins on the main window.It seems quite strange!
    There is somthing must be parallelism between the netlist and the
    LEF?I only known the name of macro in LEF must the same as verilog's
    module,and the pins of macro are parallelism to the pins of standard
    cell.
    Is other constraint?
    Thanks!
     
    Echo, Feb 18, 2004
    #1
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads

  1. SoC Encounter

  2. What do these two tools used in?? (1st Encounter / Soc Encounter)

  3. problem with verilog-in in when using arithmetic shift in verilog vode.

  4. soc encounter verilog netlist bug

  5. soc encounter keeps increasing the density

  6. Problems with soc encounter output to Magic

  7. Problem with SoC Encounter 7.1

Loading...