IC5141 - Solaris Hi , Recently we have been having a problem with VXL placing cells off grid when performing a "Gen from Source" or "Update Components and Nets". We have not seen this before on this PDK which has been used on this and older Cadence versions. The designer has his layout grid set to 0.05 x 0.05 as a default ".cdsenv" but the cells are being placed on a 0.025 grid. Has anyone else had this problem or is there another variable that needs to be set to fix this? Thanks in Advance, Tim