Virtuoso: missing solder...not missing

Hi.

I try to ask here, because I'm going crazy.

I have this Pixel schematic. Until last friday the simulations of the
schematic view were working perfectly. Friday, ADE, for some reasons,
decide to doesn't work anymore: when I run the simulation I have this
error: Failed to partition the design.

ERROR (ADE-3010): Cannot create and partition the design.
ERROR (ADE-3009): There are errors in the designs. Fix these before
netlisting.

First: I made no change in my design, so I can't really understand why
Thursday the simulations were working and Friday not...but, let's say
that something strange is going on and a ghost has modify my
schematic.

Now, if I check the schematic I have 9 warning in one block called
Controller: in the Virtuoso log window I can see that there are
warnings like this:

Warning: Solder dot on cross over at ( 26.2500, 13.1250 ).

The problem is that if I open the schematic and try to see where are
these warning...well, the solder are there!

(specification: Controller's schematic has been produced from a
Verilog netlist, but neither the verilog nor the schematic have been
modified).

Do you have any thoughts?

Thanks in advance

Francesco.

(personal comment: I started working through IC design flow 2 months
ago...I hope things will be a little bit easier in the future,
otherwise I can predict a suicide here )

 

Hi Francesco,

There must be a silly mistake somewhere ...

1. Warning: Solder dot on cross over at ( 26.2500, 13.1250 ).
You can get rid of this warning by doing the following from your
Virtuoso Schematic window:
Go to menu Check >=-> Rules Setup. In the Setup Schematic Rules Check
form, click the 'Physical' tab and then switch the 'Solder On
CrossOver' to 'ignored' instead of 'warning'.
This would disable this warning. If you want to make this option
available all the time, then I'd advise you creating a file called
'.cdsenv' in your UNIX home directory and add the following:
schematic srcSolderOnCrossover cyclic "ignored"

I'm doubting the above warning was responsible of your ADE crash. ADE
shouldn't crash on such a warning.
To solve your ADE problem, I'd proceed as following:
1. Check and save you design. You may check the entire hierarchy using
meny Check -> Hierarchy. Look at you CIW for any errors that might
occur.
2. Go to ADE -> Simulation -> Netlist -> Recreate
3. Run the simulation.

If the above does not solve the problem, then
1. Shut down you Cadence session altogether
2. Delete your simulation directory.
3. Start a new UNIX terminal.
4. Browse to your project directory and source whatever file that
allows you loading your Tools, PDKs ... etc.
5. Launch Cadence.
6. Open your design again -> Open ADE and move forward with the next
Steps.

If the above does not work then .... you may tells us more about your
stuff, but don't commit a suicide ...

Cheers,
Riad.

 

[cut]

Hi Riad,

as always thanks for help

I tried everything you said, but still the simulation is not working.
In the CIW window I have a bunch of warning like this one:

*USRWARN: Terminal in, of instance I1 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
spectre verilog verilog2 functional verilogams cmos_sch cmos.sch
extracted veriloga primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic spectre verilog
verilog2 functional verilogams cmos_sch cmos.sch extracted veriloga
primitive.
Please run Schematic Hierarchical Checker.

Now, I tried to dig in deep in this error but honestly it is a bit
hard to understand. I mean: the component exists in the scehmatic
(obviously) but all the connections are ok, and I can't understand why
ADE is complaining about it.

Others (maybe) useful informations: I tried to run the simulations
from another PC (the one where my supervisor is working(, and they
run! So, it seems that the problem is local to my settings or to my
environment...what could I check?

The only thing that comes to my mind is that something was going wrong
with the new PDK that has been installed last week. I changed my
settings as my supervisor told me, but...who knows, maybe there is
still something to do (but it would be strange because all is going on
ok in my supervisor's PC, as I said).

Well, I can imagine that it is really difficult to debug

Thanks again

Francesco.

 

[cut]

An additional information: all the warnings I have during the
netlisting performed by ADE are referred to the same Library
NikhefWork...a problem in the permission of the library, maybe?

Francesco.

 

Hi Francesco,

A bit hard to sort out this remotely ...
You said it worked fine from your supervisor's PC, was that using your
UNIX account or your supervisors ?
How do you share the data between you and your supervisor ? Are you
using any data management system, like designSync for example ?
What if you recreate the config view altogether ?

Since your supervisor is able to run the simulation properly, then I'd
advise comparing your environment to his. Just check you are pointing
to the same PDKs, libraries ... etc.
I'm afraid I have not got all the tools to remotely debug your design
remotely. Best is to ask your supervisor for help. I'm sure your
problem is rather tied to the environment/PDk rather than the tool
itself.

You might want to share your CDS.log.
Andrew may have better ideas to help you I suppose. Today is a public
holiday in the UK though ...

Cheers,
Riad.

 

Hi.

I know that is difficult, but thanks for your help

My supervisor was using his account. He simply run again the
simulation.

No. There are 4 people working on this project, but everyone is
working in a different library (we are working on different parts). He
used a library that has never been modified since a couple of months
(the same library I tried to use)

Nothing changes.

We think the same. This is my last trial: I create a new working
directory (let's say: previously I was working in test1, so in a Unix
shell I called this directory and then run the command 'virtuoso').
Now, I've created a new directory (test2) and in this directory I put
the following files:

lib.defs
cds.lib

(because here I have the path to all the library I need: these files
are from my previous directory).

display.drf
local.rsf
..cdsenv
..cdsinit
..simrc

These files are from my supervisor environment (so, for what I can
understand, me and him now have the same environment, with the same
configuration files).

But still, if I run the simulation using the schematic view, ADE
cannot partition the design.

Here, I post the complete log of the CIW window. (from the beginning
to the error. The passage are: open virtuoso, open the config file,
run the simulation. All the warning you can see have always been there
- or, at least, I've always seen many warnings similar - excpet, of
course, the list of warnings that are in the shape "USRWARN: terminal
etc..."




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Program: @(#)$CDS: virtuoso version 6.1.3 09/08/2008
02:56 (cic612lnx) $
Sub version: sub-version IC6.1.3.1 (32-bit addresses)
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dfII/local/.
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//
// Calibre Skill Interface * (v2008.3_25.16) *
//
// Copyright Mentor Graphics Corporation 2005
// All Rights Reserved.
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
// OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
//
//
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Trying to find free socket ...
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host lamone.
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and ./.cdsinit for your local technology settings
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Initializing IBM_PDK functions
IBM_PDK skill procedures for Cadence 6.1 - Jul 8 15:56:51 2009
Licensed Materials - Property of IBM - All Rights Reserved
Copyright: International Business Machines Corporation, 2009
This Material may not be copied without the written consent of
Semiconductor Research and Development Center, IBM Corp., Essex
Junction, VT 05452-4299.
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(deLicense-3) Could not get a license for Schematics L. Trying a
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Schematics L
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(deLicense-6) Checked out the license for ADE GXL to run ADE L
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Loading mmsimenv.cxt
msp: The default value of the variable "simReNetlistAll" has been
overridden.
Loading spectreMixi.cxt
Delete psf data in /tmp/fzappon/simulation42/pixel_test_hit/
spectreVerilog/config/psf.
generate netlist...
partition...
*USRERR: Module DFFRX1TF, lib NikhefWork, view schematic,
configViewString schematic verilog verilog2 functional cmos_sch
cmos.sch veriloga spectre primitive
has not been extracted. Please run schematic extraction.
*USRWARN: Terminal vdd_dig, of instance I36 (referring to placed
master NikhefWork.DFFRX1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module DFFRX1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I36 (referring to placed master
NikhefWork.DFFRX1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module DFFRX1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal CK, of instance I36 (referring to placed master
NikhefWork.DFFRX1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module DFFRX1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal QN, of instance I36 (referring to placed master
NikhefWork.DFFRX1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module DFFRX1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal D, of instance I36 (referring to placed master
NikhefWork.DFFRX1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module DFFRX1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal Q, of instance I36 (referring to placed master
NikhefWork.DFFRX1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module DFFRX1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal RN, of instance I36 (referring to placed master
NikhefWork.DFFRX1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module DFFRX1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRERR: Module level_shifter, lib NikhefWork, view schematic,
configViewString schematic verilog verilog2 functional cmos_sch
cmos.sch veriloga spectre primitive
has not been extracted. Please run schematic extraction.
*USRWARN: Terminal _out, of instance I25 (referring to placed master
NikhefWork.level_shifter.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module level_shifter, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I25 (referring to placed master
NikhefWork.level_shifter.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module level_shifter, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_dig, of instance I25 (referring to placed
master NikhefWork.level_shifter.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module level_shifter, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I25 (referring to placed
master NikhefWork.level_shifter.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module level_shifter, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I25 (referring to placed master
NikhefWork.level_shifter.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module level_shifter, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I25 (referring to placed master
NikhefWork.level_shifter.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module level_shifter, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRERR: Module AND2X1TF, lib NikhefWork, view schematic,
configViewString schematic verilog verilog2 functional cmos_sch
cmos.sch veriloga spectre primitive
has not been extracted. Please run schematic extraction.
*USRWARN: Terminal vdd_dig, of instance I31 (referring to placed
master NikhefWork.AND2X1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module AND2X1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I31 (referring to placed master
NikhefWork.AND2X1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module AND2X1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal B, of instance I31 (referring to placed master
NikhefWork.AND2X1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module AND2X1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal Y, of instance I31 (referring to placed master
NikhefWork.AND2X1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module AND2X1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal A, of instance I31 (referring to placed master
NikhefWork.AND2X1TF.symbol), residing in cellview
(NikhefWork.oscillator.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module AND2X1TF, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRERR: Module inv_osc, lib NikhefWork, view schematic,
configViewString schematic verilog verilog2 functional cmos_sch
cmos.sch veriloga spectre primitive
has not been extracted. Please run schematic extraction.
*USRWARN: Terminal sub, of instance I13 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I13 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I13 (referring to placed
master NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I13 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I13 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal sub, of instance I12 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I12 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I12 (referring to placed
master NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I12 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I12 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal sub, of instance I11 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I11 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I11 (referring to placed
master NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I11 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I11 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal sub, of instance I10 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I10 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I10 (referring to placed
master NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I10 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I10 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal sub, of instance I9 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I9 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I9 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I9 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I9 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal sub, of instance I4 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I4 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I4 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I4 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I4 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal sub, of instance I3 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I3 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I3 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I3 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I3 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal sub, of instance I2 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I2 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I2 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I2 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I2 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal sub, of instance I1 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I1 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I1 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I1 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I1 (referring to placed master
NikhefWork.inv_osc.symbol), residing in cellview
(NikhefWork.inv_osc_9.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc, lib NikhefWork,
view schematic, configViewString schematic verilog verilog2 functional
cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRERR: Module inv_osc_slow, lib NikhefWork, view schematic,
configViewString schematic verilog verilog2 functional cmos_sch
cmos.sch veriloga spectre primitive
has not been extracted. Please run schematic extraction.
*USRWARN: Terminal sub, of instance I13 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I13 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I13 (referring to placed
master NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I13 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I13 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal sub, of instance I14 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I14 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I14 (referring to placed
master NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I14 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I14 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal sub, of instance I15 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I15 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I15 (referring to placed
master NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I15 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I15 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal sub, of instance I1 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal subcon, of instance I1 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal vdd_osc, of instance I1 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal out, of instance I1 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*USRWARN: Terminal in, of instance I1 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
verilog verilog2 functional cmos_sch cmos.sch veriloga spectre
primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic verilog
verilog2 functional cmos_sch cmos.sch veriloga spectre primitive.
Please run Schematic Hierarchical Checker.
*Error* Failed to partition the design.
...unsuccessful.
ERROR (ADE-3010): Cannot create and partition the design.
ERROR (ADE-3009): There are errors in the designs. Fix these before
netlisting.
...unsuccessful.



The funny thing is that the schematic simulation doesn't work because
of this "partition" problem, instead the extracted simulation (see my
previous post, where you helped me) is working (I mean: the simulator
is able to extract the netlist and run the simulation) but I still
have problems with the power and ground connection...ok, it is not so
funny

Thanks, as usual (I owe you many, many beers )

Francesco.

 

[cut]

Ok, just to inform you: we finally solved the problem. The problem was
in a wrong library path, in the NikhefWork: basically, it was pointing
to an old version and because of the last week change in the PDK maybe
something went wrong (actually, I'm not sure of the explanation, but
now the simulations are working again and I'm more happy )

Thanks for help!

Francesco.

 

Hi

There must be a silly mistake somewhere ...

1. Warning: Solder dot on cross over at ( ... ).
You can get rid of this warning by doing the following from your
Virtuoso Schematic window:
Go to menu Check >=-> Rules Setup. In the Setup Schematic Rules Check
form, click the 'Physical' tab and then switch the 'Solder On
CrossOver' to 'ignored' instead of 'warning'.
This would disable this warning. If you want to make this option
available all the time, then I'd advise you creating a file called
'.cdsenv' in your UNIX home directory and add the following:
schematic srcSolderOnCrossover cyclic "ignored"

I'm doubting the above warning was responsible of your ADE crash. ADE
shouldn't crash on such a warning.
To solve your ADE problem, I'd proceed as following:
1. Check and save you design. You may check the entire hierarchy using
meny Check -> Hierarchy. Look at you CIW for any errors that might
occur.
2. Go to ADE -> Simulation -> Netlist -> Recreate
3. Run the simulation.

If the above does not solve the problem, then
1. Shut down you Cadence session altogether
2. Delete your simulation directory.
3. Start a new UNIX terminal.
4. Browse to your project directory and source whatever file that
allows you loading your Tools, PDKs ... etc.
5. Launch Cadence.
6. Open your design again -> Open ADE and move forward with the next
Steps.

If the above does not work then .... you may tells us more about your
stuff, but don't commit a suicide ...

Cheers,