Virtuoso - layout editor - Global Pins

Hello,
I have a problem with global pins when I try to simulate circuits that
has been extracted. It seems that my global pins are not connected
properly to the netlist extracted from the extracted circuit. the only
way I have been able to simulate such circuits was including the global
pins in the symbol. It seems easy but I have too many schematics.
is there a way to deal with that ?
I have done that previously in other cadence version and I worked properly.

Software:
IC5.032 Running in SunOS 5.8 .

Thanks in advance
Juan F. Osorio

 

Hi,

If you use Assura as extraction tool and the inherited connection
method for your globals add in your layout pin, with
edit object properties, the net expression property and the default
value for it.

Bernd

 

This sounds like the pins are not flagged as being global in the
database. I have seen this when the name of the pin does not end with a
bang (!), so the pin was not marked as being in a global net. Using VDD
as the global net name instead of vdd! is one example of this.

Another problem that sounds similar, but I don't think applies in your
case, is using labels in the layout to name nets. Even if the label has
something like vdd!, the net is not marked global.

I would open one of the layout views, select a pin that is not working
as you expect, then enter in the CIW the following command to make sure
the net the pin is in has been marked global.

geGetSelectedSet()~>pin~>net~>signals~>isGlobal