VHDL configuration

Discussion in 'Cadence' started by yaseenzaidi, Aug 23, 2007.

  1. yaseenzaidi

    yaseenzaidi Guest

    Hello

    Does NCVHDL expect top level design as configuration? This could be
    related to IEEE compliance. I have two vhd files - a module and it's
    testbench. The module elaborates fine but does not simulate on
    Simvision unless at top level I use another vhd file with
    configuration for binding the module i.e., the design project becomes
    three files.

    Is it possible to simulate a module with it's testbench without
    configurations? I'm on 05.70-s005.

    Yaseen
     
    yaseenzaidi, Aug 23, 2007
    #1
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