I have declared the following statements in a VerilogA module: ================= real try[0:4]; try[0] = 2.0; ================= However, the VerilogA parser from Cadence gives me the following errors Error found by spectre during SpectreHDL compile. "myModel/veriloga/veriloga.va", line 42: "try[<<--? 1] = 2.0;" "myModel/veriloga/veriloga.va", line 42: Error: syntax error Could someone suggest as to why this is happening. Any help is much appreciated. thanks, cupric
You didn't show the whole module, but you can only modify variables in an initial, always or analog block. It looks as if you're doing it straight after defining it? Read the Verilog-A documentation in cdsdoc, it's a good start. From what I've seen of it, "A Designer's Guide to Verilog-AMS" by Ken Kundert and Olaf Zinke (Kluwer Academic Publishers), due out in June, will also be a very useful resource for learning Verilog-A and Verilog-AMS. Regards, Andrew.