Verilog-2001 `define expressions?

Discussion in 'Cadence' started by toby, Dec 6, 2003.

  1. toby

    toby Guest

    I was trying to use a macro 'expression' --

    `define MAXIMUM2( x, y ) ( ((x)>(y))?(x):(y) ) // return greater value

    parameter A_W = 10; // Abus width (#bits)
    parameter B_W = 12; // Bbus width (#bits)
    parameter C_W = `MAXIMUM2( A_W, B_W ); // Cbus: intersect(A_W, B_W)

    This works in NC-Verilog 4.0, Modelsim 5.6, Design Compiler 2003.06, and
    Ambit/PKS 5.0. Xilinx ISE 6.1i's "XST" doesn't like it. Overall, so
    far so good!

    Then I tried to get more clever ...

    `define MAXIMUM3(x,y,z ) ( (`MAXIMUM2(x,y)>z) ? (`MAXIMUM2(x,y)):(z) )

    This barfs on most of the above...

    Do any Verilog tools support nested MACROs?

    ('common, C-programmers have been doing this sort of #define stuff for
    ages!)

    Also don't worry...I'm not using the MACROs to evaluate combinational
    exprsesions. I use the MACROs in parameter definitions. (I have some
    data-bus width conversions in a few datapath modules. Each 'node' needs
    to be sized to the larger of the 2 endpoints.)
     
    toby, Dec 6, 2003
    #1
  2. toby

    Steven Sharp Guest

    Note that this could be written more compactly as

    `define MAXIMUM3(x,y,z) `MAXIMUM2(`MAXIMUM2(x,y),z)

    but this may be even less likely to work, since it involves a macro
    appearing in a macro argument, not just the expansion text.
    I will check the most recent NC-Verilog and file a bug report if
    necessary.

    Incidentally, macros with arguments were added in Verilog-1995, not
    Verilog-2001. However, a lot of tools probably didn't support them
    until they started implementing the Verilog-2001 extensions. The
    standard does not specify whether macros can be nested (i.e. whether
    the text expansion of a macro is subject to further substitution),
    but it seems like a reasonable thing to expect.
     
    Steven Sharp, Dec 8, 2003
    #2
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