TLF Power Modelling & Power Simulation

Hi!

Is there any Cadence tool that can take the synthesized netlist of some
digital circuit, load the approptiate TLF Library that includes Power
(Current, Energy) Models for the cells in the netlist, and calculate the
power trace of the digital circuit when some input values are applied to
the circuit (like in a logic simulation).

Thanks for any hints,
Thomas Popp

 

Sure! PKS does it. You just have to read in you netlist, the libraries
(with power info), the TCF (toggle count file) from your system
simulation and then report power.

 

Well, PKS calculates some overall power comsumption depending on the
TCF. What I'm actually searching for is a tool that runs some logic
simulation of a digital circuit and as a result, also a trace of the
power (current) consumed by the circuit during the simulation should be
available. This should be similar to the power traces obtained by a
transitor-level (SPICE) simulation (e.g. with the Spectre simulator).

Is there any Cadence tool to achieve such a power trace simulation
depending on TLF power models?

Thanks,
Thomas Popp

 

Since there were no more replies to my question I want to put things
more generally:

Does anyone know of a simulation tool from any vendor, that takes

- a gate-level netlist of a circuit
- some input signal (data, clock, ...)
- and a library containig an appropriate power characterization of the
gates used in the circuit

and which is then able to simulate the power consumption (waveform!) of
the circuit corresponding to the applied input signals.

Thanks again for any hints!
-Thomas Popp