Synthesis?

Hi everyone!

We currently use the ICFB suite (Viruoso/Analog Artist) to do extensive
schematic/layout design as well as simulation. However, I was wondering
if there was any mechanism within these tools to perform any of the
following:

- synthesis flow from VHDL, or
- assuming synthesis was performed with a third-party tool, use the
Cadence tools to represent particular components with a netlist (such as
an EDF-formatted netlist) for purposes of simulation in Analog Artist.

I assume you can do the latter task using the Hierarchy Editor, but I
haven't been able to try this as yet.

Also, assuming the ICFB tools can do VHDL synthesis, is there a way to
define custom technology libraries using specified standard
logic/memory/driver cells?

Thanks in advance,
-Jason

 

There are various tools for doing Synthesis on the market, although none of
these are part of the "icfb" toolset.

For example:

RTL Compiler (Cadence)
BuildGates (Cadence)
Design Compiler (Synopsys)

You can import a VHDL netlist or Verilog Netlist using
File->Import->VHDL/Verilog. Also, there is a Cadence Synopsys Interface (under
the Tools menu if my memory is correct; I'm offline at the moment) in DFII.

Synthesis isn't my core are of expertise, so just wanted to give you some
pointers in (hopefully) the right direction.

Regards,

Andrew.

 

Jason:
You can simulate RTL or a gate level netlist with spectreVerilog or
AMS Designer.

For spectreVerilog you can use Tools->import verilog to generate a
schematic from your gate level netlist. This process is known as
verilog-In. Typically the standard cell library will have "verilog"
views and you can point to the models for the verilog views by
specifying a directory for the "-y" option in
Simulation->Options->Digital from artist. Note that the verilog views
are symbols and not the actual code which I always found annoying.
So, you can create a "verilog" view for your top level digital cell
and point to it with -y. You can create a new "behavioral" view and
copy and past your code into it. You can synthesize your RTL and
verilog-in you gate level netlist and generate a schematic and set all
the gates to verilog in the HED...

In AMS Designer the verilog-In process is being replaced with ncvlog
-use5x. The use5x switch tells ncvlog to create views for your
modules in the library defined by -work. This process creates
relative symbolic links to the code instead of copying it as the
verilog-in process does. You can't use the "-y" option with AMS
Designer so the standard cell library will need views created with
ncvlog -use5x that contain the actual code for the standard cells. If
you have any user defined primitives (UDPs) you will need to compile
those with ncvlog -use5x also.