synthesis script

Discussion in 'Cadence' started by rajan, Sep 14, 2004.

  1. rajan

    rajan Guest

    Hi,

    I am synthesizing the design, which has

    The block_1 and block_2 are the sub-blocks of the complete design named as
    BLOCK.
    I have these two blocks (block_1 and block_2) synthesized already. Now I
    would like to
    include these two synthesized blocks for the complete design synthesis.

    I have a port-name "clk_in", which is only available at block_1 level, but I
    would like to constrain
    this port at the top-level synthesis. I tried the following, but it didn't
    work.
    clk_in] <<<


    Is there something wrong with the command above or is there any other
    possibility.

    Thanks in advance.
     
    rajan, Sep 14, 2004
    #1
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.