synthesis error with DC

Discussion in 'Cadence' started by rajan, Aug 30, 2004.

  1. rajan

    rajan Guest

    Hi,

    I am trying to synthesize a design with synopsys. But, keep on getting this
    error. Would anyone please make this erro message clear to me.



    Warning: Design 'design_core' has '1' unresolved references. For more
    detailed information, use the "link" command. (UID-341)
    Information: Updating design information... (UID-85)
    Allocating blocks in 'design_core'

    Error: The selector S_18 is shorted to the selector S_2.
    Resource sharing does not support operations that are
    shorted together. (SR-8)
    Error: Cannot load design 'design_core'. (DDB-76)
    0
     
    rajan, Aug 30, 2004
    #1
  2. Consider simulation before synthesis
    to correct logical errors.

    -- Mike Treseler
     
    Mike Treseler, Aug 31, 2004
    #2
  3. hi,
    seems like a net has more than one driver. You can see schematic in
    GTECH level(Design Analyzer),
    and try to find the s_18 and s_2 blocks and may be you find which net
    you are
    trying to drive double.

    Metin
     
    Metin Yerlikaya, Sep 1, 2004
    #3
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