spiral inductor layout in virtuoso

I generated a spiral inducor using asitic. And it is saved as a *.cif file.
after I imported it, cadence can not recognized it as an inductor.
What is the reason? is there any other method to produce inductor in virtioso?

Thanks!!!

 

What tool are you talking about when you say "cadence can not recognized
it as an inductor"? Asking a question with no context is next to
useless. Unless you are into abuse and want one of the people tired of
drivel questions to flame you. Try asking a question like this:

"I created an inductor layout using Asitic, then imported the CIF file
into Virtuoso. When I run Diva extraction the inductor is not recognized
as a device. It appears to be treated as interconnect.

How do I have the inductor be recognized as a device and have the
various parameters (turns, width, spacing, etc.) measured?"

You will then get an answer something like this one:

Like any device, an inductor is just some shapes in the layout that
happen to do something electrical. You have to have device extraction
rules that recognize the device from the drawn shapes and describe the
terminals so it can be connected. The fault is in your extraction rule
deck, not the Cadence tools. Talk to your PDK rule developer about how
they expect inductors to be drawn. You may find they do not support
inductor extraction, which is not a fault in the tool, just the rule
deck you are using.

 

How about the schematics? Don't he have to create somehow a cell with all
its "secret" properties so when he runs LVS (with Diva, Assura or whatever
tool he uses) the "layout" inductor and "schematics" inductor match? I bet
Diva and Assura does not extract inductors from analogLib

Hristo

 

An inductor in a schematic is no different to the tools than a FET or
any other device. A schematic is just a bunch of devices connected by
nets. Little more than a netlist with some nifty graphics. There is no
recognition processing like a layout requires. The inductor in analogLib
is seen just like every other device.

 

Have you ever tried it?

And how do you think that analogLib inductor will match to extracted
inductor?!?!?!

Hristo

 

ok it works like this :

1. schematic side :
- the schematic is netlisted in the format needed by the verification
tool
- netlisting informations are found in the components CDF in the simInfo
section.
2. layout side :
- the layout is "extracted", this means that layers are processed using
specific
rules (extraction rules) that contain information about how to
recognize
a device (MOS, inductor, etc...) and how to netlist it.
- a netlist is created.
3. comparison :
- the two netlists are matched against each other. parameters such as
width,
length and so on are compared according to specific rules (again).

it is all a matter of setup. it is perfectly possible to match a layout
inductor
to an analogLib inductor if the rules are written for this, that is if the
layout
inductor and the schematic inductor produce the same netlist entry.

in cici (?) 's case, i'd say that he's missing extract rules for his
inductance,
and that is why it is not recognized as a device but as normal metal.
he's probably using some design kit and created his own device, not
realizing that the tools are using rules that only contain description of
the kit's devices.

stephane.

 

I wrote example Diva rules to demonstrate extracting a drawn inductor
existing on a single metal layer including parameters for turn count,
average width, average spacing, and interior hole diameter. Using these
rules, a layout with a drawn metal1 inductor was successfully extracted
and LVS compared against a schematic with an instance of the analogLib
inductor symbol.