SOS! Silicon Ensemble "CONNECT RING" error

Dear all,

I am using SE, when "CONNECT RING", accept the default options(i.e.,
STRIPPE, BLOCK, IO PAD, IO PIN, FOLLOW PIN, etc)... then after long waiting,
"Phase 2: 3 connections...", finally, it says "End routing with 3 opens..."
and three CROSSES were red on my floor plan...

I lowered down my utilization rate to 60% already... what else can I do to
avoid this problem?

Thanks a lot,

-Walala

 

Also, final "verify connectivity" in SE gives 3 violation information:

"NET: Vdd! and Gnd! have antenna..."

What can I do to get rid of this problem?

Thanks a lot,

-Walalal

 

I am using SE, when "CONNECT RING", accept the default options(i.e.,

Walala,

I hate recommending reading the manuals, but I think this is what you
should do. Try to find what all this commands (options) do, and to
understand _why_ the errors arrive.

Or at least use one option at the time, and check which is causing the
problem.

Robert

 

Hi, Robert,

Thank you for your answer.

Yes, you are right. I should refer to manual... but manual cannot
always help, right? That's why we are here...

Talking about trial and error, I believe every learner did that. But
what if your design need one night for each option you try and you
need to try all the combination of the options and you have a timeline
to beat?

Alright, you say, take a small design then try. Yes, again, this is
right. I am following a workflow tutorial. I also did some small
design, e.g., 16 bit multiplier, ... for testing and studying. The
strangest thing is that they all went well smoothly... when you need
to work on large design overnight, they failed...

I have also tried to "search and repair", but there still have
thousands of violations when I "verify geometry"...

So I am posting my SOS here to ask for your help, in case some of you
went across similar problems before. I know I am not alone on this
trial and error road... Let me claim! SOS! Help me!

Thanks,

-Walala

 

You are right now. But this is very difficult to unswer you
questing without having a look at your layout and the generated
warning. There could be 1000 of possible reasons for your routing
problem. Blocked pins, bad block plecemnt, routing variables etc.
finally fake warnings coming from the unclean cell definition.
Unpossible to guess having your letter only.

[...]

Well, I used to get number of errors when routing power. The majority of
them were fake ones (coming from the bad library definition I guess).
Looking at all the other, I think the most often I got two kinds of
them:
- spacing warnings caused by improper pin definitions in the blocks;
This may happen if the pin of the block is not on the routing grid.
- unroutable pins (either blocked, or routing parameters did not
allowed to do the routing, or just the router was to stupid to do the
job).

Best regards,

Robert