Solve the DRC error in Cadence???

Hi,

I already solved all the DRC errors in my design. But the method to
solve the following problem seems stupid.

The reason for these problems is,

I use standard cells and every standard cell has the same the input
pin name and output pin name. In my design I don't want to connect
them each other. I delete them one by one. Is there any better way to
delete them?

Thanks,

Adrian

 

Pins are only collected from the top level cell. Diva does not go down
into the hierarchy looking for pins. Did you flatten the standard cells?
If you did, you should not have told the flatten command to include the
pins. All you can do is remove the pins by hand since Diva has to
believe you wanted them there if you put them there. Use the search
form. I think it is in the Edit menu.

 

Hi,

Sorry to bother you. I knew how to solve the stupid question now.

One more question. When I did DRC, no errors. Then I did Extraction in
Diva, I got the error "Terminal in the layout is not presented in the
extracted view". How can I fix it?

Thanks,

Adrian

 

"Terminal in the layout is not present in the extracted view"
Is diva's way of saying you probably have a short. This is the way it is pronounced in Transilvania.

Open the extracted view and probe where you expect this terminal, or use the short locator if you have mastered the thing, or use series resistance parasitic extraction to narrow dow to the short location...

 

I don't understand it. Could you please to tell me in more details?I
really cannot understand why this error means short.


Thanks,

 

It means there is less terminals in extracted than in layout. Because 2 terminals can not be on the same net, the extractor has to discard one of 2 terminals that are shorted.

So, did you have a short ?

 

The most common cause of this error is having a terminal with a pin on a
layer which was not specified as being connected in the geomConnect
rule. The error message includes the terminal name. Find the terminal
and it's pin shape, which usually has the same name as the terminal.
From the pin shape, determine the graphics layer. Make sure there is a
layer derivation path from the graphic layer to a connected layer in the
geomConnect. See the manual section "Connectivity Extraction Concepts"
under the heading "Labeling" for an explanation of how pins get
associated to connected layers.

One very common mistake in rule writing is to leave the well and
substrate out of the geomConnect. This causes the terminal missing error
when well and substrate pins are in the layout. The geomStamp rule is
often used to create the connections to well and substrate, but that is
too late for the missing terminal analysis in geomConnect. It is much
better to include the well and substrate in the geomConnect and use the
"soft" clause to get the soft-connect error checking people use
geomStamp for.

 

Actually it doesn't normally come about because of a short. Shorts would show up
with a different message (don't remember what off the top of my head, but it's
not this message).

See "Diva Physical Verification"'s posting in response to this - he gives a
clear description of the likely cause.

Andrew.

 

Have a look at exactly how the geomConnect command is written!

It is worth it to check that the globalLabel command is not used!!!!
This command will override the labeling that comes from the top level
only!!!!
Also check the label layers. If they are not crucial, try commenting
them out!! (or restricting them to a few layers)
(My favorite way to limit this situation is to use LPPS per layer such
as "M1" "label" for M1 .... )


Also if cells are "flattened" in macro mode, the labels may then look
like the top level.
(i.e. ivPcell = "graphic" prop )

Both these (unlikely but possible) scenarios will cause the greif
described below!!!

-- Hope you have a simpler problem!!!!

-- Gerry

 

Hi Adrian,
I think if u have standard cell based design and u connect them
manually for a big design it might give u a problem.
have u considered using auto layout tools .Coz I have my own standard
cell library and many of my cells have same input and output pin
names.But the auto layout tool places them all with no problem at all.
The tool I am talking about is "sedsm" .Once u have your standard
cells make ur design in composer .then use sedsm for layout ,there is
lot of info about sedsm on the web how to integrate it and and use it.

have fun
harry