Soc Encounter 7.1 & search and repair routing after assembleDesign

Discussion in 'Cadence' started by Mario Kirschbaum, Mar 31, 2010.

  1. Mario Kirschbaum

    Mario Kirschbaum Guest

    Dear all,

    what is the correct approach of verifying and repairing an assembled
    design after partitioning and block level implementation of each partition?
    After loading the assembled design (encounter -init dir/top.enc), a
    search and repair nanoroute run (iteration 1 to default) results in a
    warning (NRDR-175): "External routing was imported and a full chip
    verification is not done yet."
    How do I perform a full chip verification?
    verifyConnectivity + verifyGeometry + verifyProcessAntenna does not seem
    to be "full" enough, I get the warning anyway.

    I also have another short question: is there something similar to
    "nchelp" for SoC Encounter for getting help on error and warning messages?

    Thanks for any help,
    regards, Mario
     
    Mario Kirschbaum, Mar 31, 2010
    #1
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