Silicon Ensemble + Report RC

Discussion in 'Cadence' started by suresh, Jul 18, 2006.

  1. suresh

    suresh Guest

    Hi,

    I have a routed design (using silicon ensemble) to begin with to which
    I make modifications like adding additional logic (nets and components)
    afterwhich I place the design all over again and re-route. Is it
    possible to estimate congestion - in view of new nets being added? Is
    it possible to get capacitance information - using the dspf files that
    are written out? What do I look for either in a .dspf or .rspf file?

    How do i use the HyperExtract option while doing report RC - will that
    help?

    I currently have def and dspf file of design before modification and
    def and dspf file of design after modification.

    Any help would be appreciated.

    Thanks,
    Suresh
     
    suresh, Jul 18, 2006
    #1
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads

  1. Silicon Ensemble 5.4 TLF Problem

  2. Silicon Ensemble then Manual Layout

  3. SOS! Silicon Ensemble "CONNECT RING" error

  4. SOS!what can I do if Silicon Ensemble keep giving "violation" message?

  5. What's the common utilization ratio in Silicon Ensemble P&R in practice for a mid-large design?

  6. HELP ME! Just one open remaining on chip after CONNECT RING in Silicon Ensemble?

  7. silicon ensemble layout of individual modules

  8. LVS: pin layer (Silicon Ensemble 2 Virtuoso)

Loading...