Pushing simulator session variables into veriloga models?

Discussion in 'Cadence' started by Jimmy Blue, Feb 9, 2004.

  1. Jimmy Blue

    Jimmy Blue Guest

    Standard spectre setup, using veriloga "wrapper"
    about MOSFETs to add some nonideal behaviors to
    the circuit. I have hard-coded versions working.
    What I want, is to be able to alter the devices'
    behavior further, by the value of a simulator
    session variable. For example, I would like to
    vary the VT by a series voltage source to the
    FETs' gate terminal by changing session variable
    'deltaVT'.

    The veriloga docs show only one likely option for
    this, "dynamicparam", but this yields only an
    error as unsupported. Searches for "global net"
    and "global variable" return nothing. There is
    a mention of using the 'ground' statement and
    declaring multiple nets is an implied option,
    but it also mentions that these will then be
    the reference for internal operations; I do not
    want everything referred to my "pivot" variable,
    only certain elements affected by it. Is the
    "ground" statement a means to bring in in non-
    prime-ground, non-zero "global" nets?

    I want a global value to affect every device
    without having to add properties and ensure they
    all filled in, every time. A global electrical
    node / quantity or a global variable would be
    OK. Requiring changes to the netlist procedures
    and explicit passing-down is not OK, because I do
    not have access to that layer of the design kit.

    What means are there to make veriloga modules
    "see" the direction from above, as described?
     
    Jimmy Blue, Feb 9, 2004
    #1
  2. Jimmy Blue

    Jimmy Blue Guest

    The only means I have found so far is to
    add the variable as a parameter of the
    module, and pass that variable in on the
    instantiation line.
     
    Jimmy Blue, Feb 11, 2004
    #2
  3. In AMS Designer, this is done via an out-of-module reference to a module called
    "cds_globals" which contains the design variable definitions. However, I don't
    think this can be done with Verilog-A (at least not in the spectre
    implementation of Verilog-A). You have to pass parameters via instance
    parameters.

    Regards,

    Andrew.
     
    Andrew Beckett, Feb 11, 2004
    #3
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