Problem when using the cadence abstract generator

Discussion in 'Cadence' started by alexsoton, Mar 11, 2009.

  1. alexsoton

    alexsoton Guest

    I now have problems generating an abstract view of a simple inverter.
    The cadence abstract generator has three steps, pin, extract,
    abstract. After each step, a view is generated, i.e. abstract.pin,
    abstract.ext and abstract. The abstract.pin view is no difference from
    my layout view, while abstract.ext view has all my little M1 pin
    shapes converted to M1 net shapes. The final abstract view preserves
    all these M1 net shapes but converts all the other M1 drawing shapes
    to M1 blockage shape. This results disconnections for the same net.
    For example, my OUT net now has two disconnected shapes, one on M1.net
    and the other on M1.blockage. I think this should not be right.
    Anyone has any idea on the correct way to generate abstract view?
    Alex
     
    alexsoton, Mar 11, 2009
    #1
  2. alexsoton

    Marc Heise Guest

    Hi Alex,

    what do you expect from your abstract view?
    Abstracts contain: Pins, Boundaries and Blockages. They usually not need
    routing or devices. So the result you describe sounds reasonable. You
    got a pin on M1:net and all other metal shapes are blockages. So the
    placer/router which needs this abstract (or the LEF when you export it) knows
    where to connect to and where not to route to avoid shorts.
    The pin step is not changing your layout since you probably already have
    pins in your design. The pin step is needed if you work with labels on the
    shapes and would create pins out of these labels.
    There used to be a tutorial database in the IC installation showing the abstract
    generator. Check the documentation about it.

    Kind regards,
    Marc
     
    Marc Heise, Mar 12, 2009
    #2
  3. alexsoton

    alexsoton Guest

    Marc,
    Thank you very much for your reply. In the abstract view I got, for
    the VDD net, only my VDD pin is in M1.net layer whereas the rest of it
    including my VDD power rail is in M1.boundary and disconnected from
    the M1.net VDD pin. Is this right? When I did P&R, there are geometry
    DRC errors on power rails so I figured M1.boundary might act like
    blockage which prevents routing from happening. I have seen the
    Cadence abstract manual but still couldn't figure this out. Appreciate
    it if you have some time to answer my question.
     
    alexsoton, Mar 12, 2009
    #3
  4. alexsoton

    Marc Heise Guest


    Alex,

    the tool is by far too complex to teach you how to use it via this group.
    Like I said there used to be a tutorial database with practical examples under:

    <your_install_path>/tools.sun4v/dfII/samples/tutorials/abstract

    It is described in one of the appendix of the docu. Go through that, please.

    And of course there are options to translate the complete powerrail as pin.

    Kind regards,
    Marc
     
    Marc Heise, Mar 12, 2009
    #4
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