Problem running very basic LVS

Hello all!

I am trying to learn how to do LVS by following the "Cell Design
Tutorial" on the Cadence documentation, which uses a very simple 2-
input mux as example. Everything went fine up to the DRC, but I
started having trouble on the LVS phase. The LVS failed with the
following errors (si.log):
....
Begin netlist: Nov 7 03:59:41 2007
view name list = ("auLvs" "extracted" "schematic")
stop name list = ("auLvs")
library name = "tutorial"
cell name = "mux2"
view name = "extracted"
globals lib = "basic"
Running Artist Flat Netlisting ...
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
global error:
Cannot find switch master cell for instance +13 in cellView (mux2
extracted) from viewlist 'auLvs extracted schematic ' in library
'tutorial'.
....(same error repeated for every mos instance in the extracted
view)...

Research on the web lead me to think that this was due to netlisting
errors. When I look at the properties of the transistors in the
extracted view, they all are "ivpcell" views and not "auLvs". Despite
I don't yet understand view lists, I tried creating a .simrc file with
the following contents:

lvsLayoutViewList = '("ivpcell" "auLvs" "extracted" "schematic")
lvsLayoutStopList = '("ivpcell" "auLvs")
lvsSchematicViewList = '("auLvs" "schematic")
lvsSchematicStopList = '("auLvs")
lvsLayoutVersionName = nil
lvsSchematicVersionName = nil

Now the "invalid cell view" warnings are gone, but then the LVS fails
with other errors:

Begin netlist: Nov 7 04:12:16 2007
view name list = ("ivpcell" "auLvs" "extracted" "schematic")
stop name list = ("ivpcell" "auLvs")
library name = "tutorial"
cell name = "mux2"
view name = "extracted"
globals lib = "basic"
Running Artist Flat Netlisting ...

*Error* Cell: pfet in library: sample is missing a simInfo section
in it's CDF for the current simulator.
*Error* artIsCallablep: argument #1 should be either a string or a
symbol (type template = "S") - nil
error in instance path /+13:
Error in evaluating property value: 'ancNetlistFileInstOutput()'.
....(same error repeated for all pmos instances)...

*Error* Cell: nfet in library: sample is missing a simInfo section
in it's CDF for the current simulator.
*Error* artIsCallablep: argument #1 should be either a string or a
symbol (type template = "S") - nil
error in instance path /+6:
Error in evaluating property value: 'ancNetlistFileInstOutput()'.
....(same error repeated for all nmos instances)...

One last weird observation. All the instances in the extracted view
belong to library named "sample", and not to the "pCells" library, as
(I guess) one would expect. Transistor cells in the the "sample" lib
don't have 'auLvs' views, while the ones in the "pCells" lib have both
'auLvs' and 'ivpcell' views. ...Clueless about which one is the
correct one nor what are the differences between these two types of
views... *sigh*

It seems I am missing some basic configuration. BTW, I already checked
the 'CDS_Netlisting_Mode' is (properly?) set to 'Analog'. Any ideas on
what could be the problem? Thanks in advance for any help, and sorry
for the repeatedly long posts.

Regards,

Jorge.

 

Hi,

what does your design flow look like?
By that I mean, which tools and version of tools are you using?

 

Thanks so much for your reply, Svenn. I am using IC 5.10.41.500.3.49
with no comercial design kit; I just copied to my working directory
the libraries provided in the tutorial path "$IC/tools/dfII//samples/
tutorials/le", and followed all the steps as stated in the "Cell
Design Tutorial, Product Version 5.0" document. I am running the
layout tool by means of the "layoutPlus" command and the LVS through
the "Verify->LVS" menu option.

Regards,

Jorge Luis.

 

Well, I am more acustomed to assura so I think someboy else must help
you out here as I don't know that flow.

 

Don't worry Svenn; I finally found the problem. It turned out that all
the mess was due to miss-setting "CDS_Netlisting_Mode" to "Analog".
Either by setting it to "Digital" or by not setting it at all, the LVS
went like breeze. I still largely ignore the subtleties between these
two netlisting modes (or should I say three modes, counting the unset
mode as a third option?); maybe I should post a new entry asking for
some straight-to-the-fact explanations on this topic.

Thanks anyway for your interest!

Regards,

Jorge.

 

Don't worry Svenn; I finally found the problem. It turned out that all

For the record :

Your issue is covered in sourcelink solution #11013422. It is explained that in Analog mode, the
stopping view is set to 'auLvs', while it is set to 'lvs' in Digital mode. Since the components in
the sample library have no auLvs view, this causes the error.



Stéphane

 

Note also that CDS_Netlisting_Mode being unset is exactly the same as "Digital".
The reason why this is the default is largely historical, and I'd say the vast
majority (but not all) Cadence IC users use it in "Analog" mode.

The main difference between Analog and Digital mode is that affected netlisters
(primarily auCdl vs cdl and auLvs vs lvs) use either CDF information for
netlisting (in Analog mode) or properties on the stopping view for netlisting
(in Digital mode). It also affects whether doing instId~>myProp will get the
value of myProp from the CDF defaults if it's not present on the instance (it
does this in Analog mode, but not Digital). There's also another mode
"Compatibility" which is a sort of hybrid of the two (or the worst of both
worlds, depending on your point of view!).

It's just that the cell design tutorial expects it to be in "Digital" mode...

Regards,

Andrew.

 

Thanks for your insteresting remarks, Andrew. Could you point me to
any cadence documentation that explains these issues and/or the
netlisting concepts with an instructive approach? That would be just
great.

Regards,

Jorge Luis.

 

CDS_Netlisting_Mode is documented in several places, but a good
place is probably <instdir>/doc/anasimhelp/anasimhelp.pdf in the
Environment Setup chapter.

Regards,

Andrew.

 

Perfect; thanks so much for the link. I already got into it.

Regards,

Jorge.

 

Even though you got gereat info.. The error was the stoplist statment.
;')