New book: SystemVerilog Assertions Handbook

Discussion in 'Cadence' started by vhdlcohen, Dec 1, 2004.

  1. vhdlcohen

    vhdlcohen Guest

    I am pleased to announce the release of our new book
    SystemVerilog Assertions Handbook which addresses SVA Assertion-Based
    Verification language along with pragmatic applications and guidelines
    in the use of SystemVerilog Assertions.

    For more information on the book, please read the preface / backcover

    Ben Cohen
    Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
    * Co-Author: Now available: "SystemVerilog Assertions Handbook", ISBN
    * Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
    vhdlcohen, Dec 1, 2004
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