NCSim and SystemVerilog support?

Hi,

When use NCSim5.7_s001, I found SystemVerilog class cannot be compiled.
For example,
ncvlog/EXPMPA =
Section [A.1] of the LRM defines the syntactic structure of
Verilog. At the highest level, a 'description' begins with
the keyword 'module', 'macromodule' or 'primitive'. One of
these words was not found. Check your spelling and file
organization.


What's the latest version of NCSim and how about SystemVerilog support?

BTW, Cadence's SourceLink website is too poor to tolerate (always break
and cannot see the webpage)!

Best regards,
Davy

 

The latest is 5.82_s002. That version does allow you to use classes.
5.83 was supposed to be out Oct. 31, then Nov 14th, but now it's
dropped off of the current release cycle as published on Sourcelink.

Consider it a blessing when it fails to compile giving an error
message. The biggest problem I've had with SystemVerilog is with fatal
tool crashes and you have absolutely no idea where the problem is. When
that happens, I just start commenting code out until it starts working.

David Walker

 

Hi David,

Cadence engineer said 5.83 is a milestone in SystemVerilog support. And
I am waiting for it. Now I have to enclose class in module/program, and
cannot do reuse.

Hope NCsim be better.

Best regards,
Davy