LVS Failure from wrong Terminal or Pin order in auCdl created sourceNetlist

Hello,

I'm having trouble getting a simple buffer (two inverters) to LVS and
I've figured out the Calibre LVS tool is working properly, but the
source netlist it uses is incorrect. It uses auCdl to create the
netlist and I've tried creating the netlist from the CIW using File-

the following warnings:

Running Artist Hierarchical Netlisting ...

*WARNING* *Warning* Could not determine the node name for terminal
'"gnd"'. This may be caused by an error in the CDF specified on:
component : inv_1x
in cellview : schematic
of library : MCSG90nm_StdCells
*Warning* Could not determine the node name for terminal '"vdd"'. This
may be caused by an error in the CDF specified on:
component : inv_1x
in cellview : schematic
of library : MCSG90nm_StdCells
End netlisting May 12 14:58:43 2008



The netlist (which I've pasted below) defines the inverter sub
circuits, but then when it refers to the inverters to create the
buffer, the pin order is completely wrong so that inverter inputs and
outputs are tied to ground, while the input and output signals go to
what should be power and ground sources/drains. I am trying to use
inherited connections as used in the latest tutorial on Sourcelink, so
my inverter schematic has power and ground pins defined as [@vdd:
%:vdd!] and then I have an inverter symbol (used in my buffer
schematic) that doesn't have power, gnd pins, but I define the power
supply to vcc! with a netset property. The schematic does netlist and
simulate correctly when I netlist for spectre (netlist included at the
bottom)

I searched the group and found a similar issue (http://tinyurl.com/
5u97e7) where the auCdlCDFPinCntrl variable was changed in
the .simrc, but setting the variable to 't or 'nil doesn't make a
difference. I'm using ICFB version 5.10.41_USR5.90.69 (32-bit
addresses) on RHEL 3. I appreciate any suggestions.

Thank you,

Justin
************************************************************************
* auCdl Netlist:
*
* Library Name: play90nm
* Top Cell Name: buffer_1x1x
* View Name: schematic
* Netlisted on: May 12 14:58:43 2008
************************************************************************

..PARAM

*.GLOBAL vcc!
+ gnd!

*.PIN vcc!
*+ gnd!

************************************************************************
* Library Name: MCSG90nm_StdCells
* Cell Name: inv_1x
* View Name: schematic
************************************************************************

..SUBCKT inv_1x in out inh_gnd inh_vdd
*.PININFO in:I out:O inh_gnd:B inh_vdd:B
MM1 out in inh_vdd inh_vdd pch l=100n w=600n m=1
MM0 out in inh_gnd inh_gnd nch l=100n w=200n m=1
..ENDS

************************************************************************
* Library Name: play90nm
* Cell Name: buffer_1x1x
* View Name: schematic
************************************************************************

..SUBCKT buffer_1x1x in out
*.PININFO in:I out:O
Xinv_1x1 gnd! net6 out vcc! / inv_1x
Xinv_1x0 gnd! in net6 vcc! / inv_1x
..ENDS

// Generated for: spectre
// Generated on: May 9 15:23:39 2008
// Design library name: play90nm
// Design cell name: buffer_1x1x
// Design view name: schematic
simulator lang=spectre
global 0 vcc!


// Library name: MCSG90nm_StdCells
// Cell name: inv_1x
// View name: schematic
subckt inv_1x inh_gnd in out inh_vdd
M0 (out in inh_gnd inh_gnd) nch l=100n w=200n m=1 ad=4.6e-14 \
as=4.6e-14 pd=860.0n ps=860.0n nrd=0.65 nrs=0.65 sa=2.3e-07 \
sb=2.3e-07
M1 (out in inh_vdd inh_vdd) pch l=100n w=600n m=1 ad=1.38e-13 \
as=1.38e-13 pd=1.66u ps=1.66u nrd=0.216667 nrs=0.216667
sa=2.3e-07 \
sb=2.3e-07
ends inv_1x
// End of subcircuit definition.

// Library name: play90nm
// Cell name: buffer_1x1x
// View name: schematic
inv_1x1 (0 net6 out vcc!) inv_1x
inv_1x0 (0 in net6 vcc!) inv_1x