LVS expert! Issue with LVS-ing Standard Cells

Discussion in 'Cadence' started by Szekit, Nov 5, 2004.

  1. Szekit

    Szekit Guest

    When I CDL in a standard cell, Cadence messed up the drain and source
    connections of the transistor as the following:

    ..SUBCKT NAND2 A B Y
    MM6 VDD! B Y VDD! P W=3u L=180.0n M=1
    MM7 VDD! A Y VDD! P W=3u L=180.0n M=1
    .....
    .....
    ..ENDS

    Instead of "Y B VDD! VDD!" for the P-channel devices, it swapped the
    the drain and source connection to "VDD! B Y VDD!".

    For simulation, it seems okay because it's a switch to VDD. However,
    does it pose any problem for LVS??

    Thanks!!
     
    Szekit, Nov 5, 2004
    #1
  2. What you describe is much like what happens during device extraction
    from layout. There is no way to orient the source and drain along the
    current flow, so the connections are assigned arbitrarily. LVS
    understands the S/D permutability of a MOS device and handles it without
    any trouble.

    The only case where I have seen problems is when a user wanted to
    consider the parasitic characteristics of the S/D regions as
    differentiators. It is not possible to know if LVS has done a S/D swap,
    so you cannot check the parasitic values are correct. I've only seen
    this in memory cores, which are so rigid in their design there is little
    point to be checking them.
     
    Diva Physical Verification, Nov 5, 2004
    #2
  3. Szekit

    fogh Guest

    most likely your pmoses have a completely simetric layour for source and
    drain, so that the distinction is electrical, but not physical.
    Only in some special devices, with drain enhanced FET (for reduced hot carrier
    effects) or gradual doped channels (for maximum speed) do you have a physical
    difference between S and D.
     
    fogh, Nov 8, 2004
    #3
  4. Szekit

    Szekit Guest

    Thank you all! Good information.

     
    Szekit, Nov 9, 2004
    #4
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