LVS between DFII schematic and layout using Assura

Discussion in 'Cadence' started by Min Pan, Jul 9, 2003.

  1. Min Pan

    Min Pan Guest

    Hello all. I have run into a problem with Assura.

    Now I'm trying to do the LVS between the dfII schematic and layout.
    When I run the Assura LVS, it always fail. I have checked the log
    file. It seems that when Assura running the Nvn PreExtraction, it
    tried to using dfIItoVldb to translate the schematic to vldb netlist
    and caused some error. It gave the error message like the following.
    --------------------------------------------------------------------
    Library Name: "ami500mxsc5"
    Cell Name: "inv1"
    Cell View: "schematic"
    Output Data Base Name: "/home/panmin/ami500mxsc5/lvs/inv1/inv1.sdb"
    Simulator Name: "auLvs"
    View List: "auLvs schematic symbol"
    Stop List: "auLvs"
    Net Listing Mode is Analog
    writing /home/panmin/ami500mxsc5/lvs/inv1/inv1.sdb
    inputting /home/panmin/ami500mxsc5/lvs/inv1/inv1.sdb
    Error - There can only be one vldb netlist in one network.
    ------------------------------------------------------------------------

    I can't figure out why it always said "There can only be one vldb
    netlist in one network." The Assura version is 3.0.

    Any help is appreciated.

    Thanks.

    Min Pan
    e-mail:
     
    Min Pan, Jul 9, 2003
    #1
    1. Advertisements

  2. Min Pan

    Jay Lessert Guest

    I think because you've got something interesting going on, either
    in the avCompareRules( schematic() ) section of your .rsf, and/or
    in your .vlr.

    I know this happens if you try to mix dfII and Verilog directly
    from the GUI. Though it doesn't sound like you would be doing
    this, for a single inverter. :)

    So show us the little "extra" avCompareRules()
    block down at the bottom of your .rsf, and the full content
    (should be small) of the associated .vlr.

    -Jay-
     
    Jay Lessert, Jul 9, 2003
    #2
    1. Advertisements

  3. Min Pan

    Jay Lessert Guest

    The extract.rul and binding file cannot affect it.

    The compare.rul file technically could, if you put a
    schematic(netlist()) section in it, right? Could happen
    if one was careless with cut'n'paste.
    These are fine.

    -Jay-
     
    Jay Lessert, Jul 13, 2003
    #3
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.