license feature number mapping?

Where do I find a document that maps the license feature number to a
description of what it is. For example, I know that 34510 is ADE but
I don't know what 365, 370, 14140, ... are.

 

when you receive the license files, there is a file called
"product_FEATURE_map.txt" this is the most detailed file
for your site.
if you just want a simple correspondance, it is somewhere
in the docs or installation tree. (I don't remember exaclty).
Repost if you cannot locate it.
HTH

 

Erik,

the partial answer is :
$(cds_root)/share/license/products.dfII

but if you look, for instance, at the new cadence download site you find
more details, so I suspect there is a better source for this mapping. I
plan to find this and add a better feature# -> name conversion to the
PHPlicensewatcher ( it is a tool from sourceforge ).

Nowadays, I don t have too much of a problem with the "feature number"
to "feature name" mapping, but I have more of a problem with the
"corporate product name" to "download product name" mapping.
Especially since the corporate names and product bundles change so
often. And the download names are 3 letters acronym that are on most web
pages unexpanded.

An illustration:
- Try for instance a search of "LDV" on the cadence corporate site: I
had one(1) hit
- then, on the download site, look at the products inside solaris-LDV,
and compare with windows-LDV
- go back to corporate site search, and try "NC-sim" "inca" "AMS"
"envisia", try to map the existing links between those, and with LDV.
connect the dots and put color inside ;-)

Even the tool names change sometimes (analog artist becomes analog
design environment, device level editor becomes virtuoso XL).

<calimero mode> I wish cadence thought less about pleasing lawyers and
PR, and more about the end-users, or even about us, poor support drones
! </calimero mode> ;-]
As for marketing, I don t know about the US or Japan, but around here
decision-makers find this "change the package and sell the same stuff" a
very cheap trick, a rather unexpected one for a market leader. That's a
shame, because some of those tools are good.

 

I got a more complete mapping (see below).

I am looking for an education in the Cadence license features, so I
asked the following to Cadence awhile back.

Assura_, IC_, SPW_, Concept_, PSPICE_, APD_, SE_, ...

map 32500 to spectre, the feature name should be more descriptive. I
should get
a description in a file that says what spectre is and which analysis
types 32500
provides.

types or does it also include the RF packaging models?

Product number Feature Description
111 111 Cadence(R) design framework II
111 plotVersa Cadence(R) design framework II
200 200 Design Entry
206 206 Virtuoso(R) simulation environment
206 plotVersa Virtuoso(R) simulation environment
207 207 Waveform
250 250 Synergy HDL Synthesizer
250 HDL-DESKTOP Synergy HDL Synthesizer
250 LEAPFROG-CV Synergy HDL Synthesizer
250 LEAPFROG-SYS Synergy HDL Synthesizer
250 plotVersa Synergy HDL Synthesizer
250 Schematic_Generator Synergy HDL Synthesizer
250 VXL-VLS Synergy HDL Synthesizer
251 251 Synergy Optimizer
251 HDL-DESKTOP Synergy Optimizer
251 LEAPFROG-CV Synergy Optimizer
251 LEAPFROG-SYS Synergy Optimizer
251 plotVersa Synergy Optimizer
251 Schematic_Generator Synergy Optimizer
251 synTiOpt Synergy Optimizer
251 VXL-VLS Synergy Optimizer
274 274 SPICE Interface with SPICE 2G.6
276 276 Virtuoso(R) schematic composer HSPICE interface
278 Composer_Spectre_Sim_Solution Virtuoso(R) schematic composer
Spectre(R) interface
279 279 Simulation & Test Language
279 plotVersa Simulation & Test Language
283 283 Open Simulation System
300 300 Virtuoso(R) layout editor
300 960 Virtuoso(R) layout editor
300 plotVersa Virtuoso(R) layout editor
302 Virtuoso_Schem_Option Virtuoso(R) Schematic Layout Option
305 305 Virtuoso(R) Compactor
314 314 Assura(TM) interactive electrical rules checker
314 plotVersa Assura(TM) interactive electrical rules checker
316 316 Assura(TM) interactive layout parameter extractor
316 plotVersa Assura(TM) interactive layout parameter extractor
318 318 Assura(TM) interactive parasitic resistance extractor
318 plotVersa Assura(TM) interactive parasitic resistance extractor
322 322 Assura(TM) interactive layout vs. schematic verifier
322 plotVersa Assura(TM) interactive layout vs. schematic verifier
336 336 Remote Diva Interface
337 hyperExtract Envisia(TM) physical design planner (Pillar)
HyperExtract parasitic extractor option
337 pillar.dpuxIn Envisia(TM) physical design planner (Pillar)
HyperExtract parasitic extractor option
370 370 Virtuoso Layout Synthesizer
371 371 Three Layer Routing Option for Virtuoso Layout Synthesizer
(370)
373 373 Timing Assurance Placement Option for Virtuoso Layout
Synthesizer (370)
374 LAS_Cell_Optimization Cell Optimization Option for Layout
Synthesizer (370)
410 CELL3 Cell3 Ensemble
410 CELL3_PR Cell3 Ensemble
501 501 ModuleMaker
550 550 Structure Compiler
550 plotVersa Structure Compiler
570 570 Virtuoso(R) schematic composer to design compiler integration
570 940 Virtuoso(R) schematic composer to design compiler integration
570 945 Virtuoso(R) schematic composer to design compiler integration
581 Vampire_HDRC Vampire(R) design rule checker
581 Vampire_UI Vampire(R) design rule checker
583 Vampire_HLVS Vampire(R) layout vs. schematic verifier
583 Vampire_UI Vampire(R) layout vs. schematic verifier
585 Vampire_RCX Vampire parasitic extractor
585 Vampire_UI Vampire parasitic extractor
681 ConcICe_Option Cadence(R) RC network reducer option
731 DRAC2CORE Dracula(R) flat design rule checker
731 DRAC2DRC Dracula(R) flat design rule checker
731 DRACDIST Dracula(R) flat design rule checker
733 DRAC2CORE Dracula(R) flat layout vs. schematic verifier
733 DRAC2LVS Dracula(R) flat layout vs. schematic verifier
733 DRACLVS Dracula(R) flat layout vs. schematic verifier
780 DRAC2CORE Dracula(R) pattern generation option
780 DRAC3CORE Dracula(R) pattern generation option
780 DRACPG_E Dracula(R) pattern generation option
900 skillDev Cadence(R) SKILL development environment
952 Composer_EDIF300_Connectivity Virtuoso(R) EDIF 300 connectivity
reader/writer
953 Composer_EDIF300_Schematic Virtuoso(R) EDIF 300 schematic
reader/writer
966 966 Keys Only APPLICON OUT
991 991 Hardcopy Intermediate File Generation
991 plotVersa Hardcopy Intermediate File Generation
995 995 HP-GL Hardcopy Output
995 plotVersa HP-GL Hardcopy Output
3000 300 Virtuoso(R) XL Layout Editor
3000 960 Virtuoso(R) XL Layout Editor
3000 plotVersa Virtuoso(R) XL Layout Editor
3000 Virtuoso_XL Virtuoso(R) XL Layout Editor
3100 Virtuoso_custom_placer Virtuoso(R) custom Placer
3200 Virtuoso_custom_router Virtuoso(R) custom router
3300 Cadence_chip_assembly_router Cadence chip assembly router
4000 virtuoso_chip_editor Virtuoso Chip Editor
11400 300 Virtuoso Mask Design System
11400 312 Virtuoso Mask Design System
11400 960 Virtuoso Mask Design System
11400 963 Virtuoso Mask Design System
11400 964 Virtuoso Mask Design System
11400 11400 Virtuoso Mask Design System
11400 plotVersa Virtuoso Mask Design System
12141 12141 Cadence(R) design framework integrator's toolkit
12500 12500 Keys Only Tancell/Cell3/Gate Ensemble Encapsulated
Graphics UI
14000 14000 Preview Front-End Floorplanner System
14000 _21900 Preview Front-End Floorplanner System
14000 LEAPFROG-CV Preview Front-End Floorplanner System
14000 plotVersa Preview Front-End Floorplanner System
14010 14010 Preview Basic Floorplanner System
14010 LEAPFROG-CV Preview Basic Floorplanner System
14010 plotVersa Preview Basic Floorplanner System
14020 14020 Preview Expert Floorplanner System
14020 _21900 Preview Expert Floorplanner System
14020 LEAPFROG-CV Preview Expert Floorplanner System
14020 plotVersa Preview Expert Floorplanner System
14040 14040 Preview Timing Budgeter
14101 14101 Cell Ensemble Option for Preview Basic (14010) or Expert
(14020)
14101 plotVersa Cell Ensemble Option for Preview Basic (14010) or
Expert (14020)
14111 14111 Block Ensemble Option for Preview Basic (14010) or Expert
(14020)
14111 plotVersa Block Ensemble Option for Preview Basic (14010) or
Expert (14020)
14120 14120 Three-Layer Routing Option for Block Ensemble (14111)
14130 14130 Timing Driven Option for Block Ensemble (14111)
14140 14140 Timing Driven Option for Cell Ensemble
14410 14410 Three-Layer Channel Routing Option to Cell Ensemble
(14101)
20235 20120 All Composer Part & Verilog Model Libraries
20235 20121 All Composer Part & Verilog Model Libraries
20235 20122 All Composer Part & Verilog Model Libraries
20235 20123 All Composer Part & Verilog Model Libraries
20235 20124 All Composer Part & Verilog Model Libraries
20235 20127 All Composer Part & Verilog Model Libraries
20235 20128 All Composer Part & Verilog Model Libraries
20235 20220 All Composer Part & Verilog Model Libraries
20235 20221 All Composer Part & Verilog Model Libraries
20235 20222 All Composer Part & Verilog Model Libraries
20235 20227 All Composer Part & Verilog Model Libraries
21060 21060 Virtuoso(R) schematic composer VHDL interface
21060 LEAPFROG-CV Virtuoso(R) schematic composer VHDL interface
21200 21200 Virtuoso(R) physical interface environment
21400 21400 Virtuoso(R) schematic composer Verilog(R) interface
21400 LEAPFROG-CV Virtuoso(R) schematic composer Verilog(R) interface
21920 21920 STL Tester Code Generators
22650 22650 VHDL Synthesizer
22650 HDL-DESKTOP VHDL Synthesizer
22650 LEAPFROG-BV VHDL Synthesizer
22650 LEAPFROG-CV VHDL Synthesizer
22650 LEAPFROG-SYS VHDL Synthesizer
22650 plotVersa VHDL Synthesizer
22650 Schematic_Generator VHDL Synthesizer
22650 synTiOpt VHDL Synthesizer
22840 Placement_Based_Optimization Envisia(TM) placement based
optimization
24015 24015 Thermax (UNIX)
24015 plotVersa Thermax (UNIX)
24025 24025 Thermax Expert (UNIX)
24025 plotVersa Thermax Expert (UNIX)
24100 24100 Thermax Model Library (UNIX)
25000 SimVision Affirma(TM) analysis environment simulation option
25050 Affirma_advanced_analysis_env Cadence(R) advanced analysis
environment
26000 100 Cadence(R) Verilog(R)-XL simulator
26000 21900 Cadence(R) Verilog(R)-XL simulator
26000 26000 Cadence(R) Verilog(R)-XL simulator
26000 Affirma_sim_analysis_env Cadence(R) Verilog(R)-XL simulator
26000 CWAVES Cadence(R) Verilog(R)-XL simulator
26000 UET Cadence(R) Verilog(R)-XL simulator
26000 VERILOG-XL Cadence(R) Verilog(R)-XL simulator
26000 VXL-VCW Cadence(R) Verilog(R)-XL simulator
26000 VXL-VET Cadence(R) Verilog(R)-XL simulator
26000 VXL-VLS Cadence(R) Verilog(R)-XL simulator
26000 VXL-VRA Cadence(R) Verilog(R)-XL simulator
26020 VXL-SWITCH-RC Switch-RC Option for Verilog-XL (26000)
26500 verifault Cadence(R) Verifault(R)-XL simulator
26510 dfsverifault Cadence(R) Verifault(R)-XL slave node license
27000 26000 Leapfrog VHDL Simulator
27000 Affirma_sim_analysis_env Leapfrog VHDL Simulator
27000 CWAVES Leapfrog VHDL Simulator
27000 HDL-DESKTOP Leapfrog VHDL Simulator
27000 LEAPFROG-BV Leapfrog VHDL Simulator
27000 LEAPFROG-CV Leapfrog VHDL Simulator
27000 LEAPFROG-SV Leapfrog VHDL Simulator
27000 LEAPFROG-SYS Leapfrog VHDL Simulator
27000 SWIFT Leapfrog VHDL Simulator
27000 UET Leapfrog VHDL Simulator
27010 VERILOG-SLAVE Leapfrog Model Import Package Option
27010 VXL-LMC-HW-IF Leapfrog Model Import Package Option
28000 100 Cadence(R) NC-Sim mixed language simulator
28000 21900 Cadence(R) NC-Sim mixed language simulator
28000 26000 Cadence(R) NC-Sim mixed language simulator
28000 Affirma_NC_Simulator Cadence(R) NC-Sim mixed language simulator
28000 Affirma_sim_analysis_env Cadence(R) NC-Sim mixed language
simulator
28000 CWAVES Cadence(R) NC-Sim mixed language simulator
28000 UET Cadence(R) NC-Sim mixed language simulator
28000 VERILOG-XL Cadence(R) NC-Sim mixed language simulator
28000 VXL-TURBO Cadence(R) NC-Sim mixed language simulator
28000 VXL-VCW Cadence(R) NC-Sim mixed language simulator
28000 VXL-VET Cadence(R) NC-Sim mixed language simulator
28000 VXL-VLS Cadence(R) NC-Sim mixed language simulator
28000 VXL-VRA Cadence(R) NC-Sim mixed language simulator
28050 Affirma_sim_analysis_env NC-Sim Desktop
28050 NCSim_Desktop NC-Sim Desktop
28200 100 Cadence(R) NC-Verilog(R) simulator
28200 21900 Cadence(R) NC-Verilog(R) simulator
28200 26000 Cadence(R) NC-Verilog(R) simulator
28200 Affirma_sim_analysis_env Cadence(R) NC-Verilog(R) simulator
28200 CWAVES Cadence(R) NC-Verilog(R) simulator
28200 NC_Verilog_Data_Prep_Compiler Cadence(R) NC-Verilog(R) simulator
28200 NC_Verilog_Simulator Cadence(R) NC-Verilog(R) simulator
28200 UET Cadence(R) NC-Verilog(R) simulator
28200 VERILOG-XL Cadence(R) NC-Verilog(R) simulator
28200 VXL-TURBO Cadence(R) NC-Verilog(R) simulator
28200 VXL-VCW Cadence(R) NC-Verilog(R) simulator
28200 VXL-VET Cadence(R) NC-Verilog(R) simulator
28200 VXL-VLS Cadence(R) NC-Verilog(R) simulator
28200 VXL-VRA Cadence(R) NC-Verilog(R) simulator
28400 Affirma_sim_analysis_env Cadence(R) NC-VHDL simulator
28400 NC_VHDL_Simulator Cadence(R) NC-VHDL simulator
28600 Affirma_equiv_checker_prep Cadence(R) equivalence checker
28600 Affirma_equivalence_checker Cadence(R) equivalence checker
28600 Affirma_sim_analysis_env Cadence(R) equivalence checker
28600 plotVersa Cadence(R) equivalence checker
29500 100 Affirma(TM) verification cockpit
29500 21900 Affirma(TM) verification cockpit
29500 26000 Affirma(TM) verification cockpit
29500 Affirma_sim_analysis_env Affirma(TM) verification cockpit
29500 CWAVES Affirma(TM) verification cockpit
29500 UET Affirma(TM) verification cockpit
29500 Verif_Ckpit_Analysis_Env Affirma(TM) verification cockpit
29500 Verif_Ckpit_Runtime_Env Affirma(TM) verification cockpit
29500 VERILOG-XL Affirma(TM) verification cockpit
29500 VXL-TURBO Affirma(TM) verification cockpit
29500 VXL-VCW Affirma(TM) verification cockpit
29500 VXL-VET Affirma(TM) verification cockpit
29500 VXL-VLS Affirma(TM) verification cockpit
29500 VXL-VRA Affirma(TM) verification cockpit
32100 OASIS_Simulation_Interface Cadence(R) analog Oasis run-time
option
32110 32110 Keys Only Opamp & Comparator Macromodel Generators
32120 Artist_Statistics Cadence(R) electronic design for
manufacturability option
32125 Corners_Analysis Cadence(R) analog corners analysis option
32130 Artist_Optimizer Cadence(R) analog circuit optimizer option
32140 32140 Cadence(R) analog mixed-signal simulation interface option
32190 32190 Switched Capacitor Filter Synthesis Option for Design
Environment (34510)
32500 32150 Spectre(R) circuit simulator
32500 32500 Spectre(R) circuit simulator
32501 32501 Spectre(R) user-compiled model interface option
32520 SpectreRF Spectre(R) RF simulation option
32600 32600 Dantes Design & Test System
32610 32610 Dantes Teradyne A510 Module
32620 32620 Dantes Teradyne A520 Module
32630 32630 Dantes LTX Synchromaster Module
32640 32640 Dantes HP9480 Model
32700 Pearl Affirma(TM) timing analyzer for full-custom design
32760 32150 Cadence(R) analog HSPICE interface option
32760 32760 Cadence(R) analog HSPICE interface option
33010 33010 Device-Level Editing Option for Layout (300)
33011 Device_Level_Placer Device Level Placer Option for Device Level
Editor (33010)
33301 33301 Cadence(R) analog mixed-signal back-annotation interface
option
34500 945 Virtuoso(R) schematic composer
34500 994 Virtuoso(R) schematic composer
34500 34500 Virtuoso(R) schematic composer
34500 LEAPFROG-CV Virtuoso(R) schematic composer
34500 plotVersa Virtuoso(R) schematic composer
34500 UET Virtuoso(R) schematic composer
34510 34510 Cadence(R) analog design environment
34511 Substrate_Coupling_Analysis Cadence(R) RF substrate coupling
analysis option
34520 283 CheckPlus Toolkit for Composer (UNIX)
34520 ComposerCheckPlus_Checker CheckPlus Toolkit for Composer (UNIX)
34520 ComposerCheckPlus_RuleDev CheckPlus Toolkit for Composer (UNIX)
34520 UET CheckPlus Toolkit for Composer (UNIX)
34530 Affirma_AMS_distrib_processing Cadence(R) analog distributed
processing option
37100 37100 Switched Capacitor Layout Generators
37500 Device_Level_Router Device Level Router
40020 40020 Keys Only EEsof Libra Simulator Interface
40030 40030 HP MNS Interface
40040 40040 Compact Software Microwave Harmonica Interface
40500 40500 Keys Only Microwave Simulation Environment
41000 41000 Keys Only Cadence(R) microwave layout component extractor
49600 Gate_Ensemble_DSM Envisia(TM) gate array place-and-route DSM
49600 GATEENSEMBLE Envisia(TM) gate array place-and-route DSM
49710 Silicon_Ensemble_CTS CTS Option for Silicon Ensemble Series
(49700/49800)
49800 Silicon_Ensemble Envisia(TM) place-and-route DSM
49800 Silicon_Ensemble_DSM Envisia(TM) place-and-route DSM
49900 Envisia_SE_ultra_place_route Silicon Ensemble(TM)
place-and-route ultra
49900 Silicon_Ensemble Silicon Ensemble(TM) place-and-route ultra
49900 Silicon_Ensemble_DSM Silicon Ensemble(TM) place-and-route ultra
49950 Envisia_SE_SI_place_route Envisia(TM) place-and-route system
with signal and design integrity features
49950 Envisia_SE_ultra_place_route Envisia(TM) place-and-route system
with signal and design integrity features
49950 Silicon_Ensemble Envisia(TM) place-and-route system with signal
and design integrity features
49950 Silicon_Ensemble_DSM Envisia(TM) place-and-route system with
signal and design integrity features
50000 945 System Workbench (UNIX)
50000 994 System Workbench (UNIX)
50000 34500 System Workbench (UNIX)
50000 50000 System Workbench (UNIX)
50000 LEAPFROG-CV System Workbench (UNIX)
50000 plotVersa System Workbench (UNIX)
50000 UET System Workbench (UNIX)
50010 50010 Composer to System Workbench Upgrade (UNIX)
50110 50110 Delay Backannotation from Allegro (UNIX)
50200 50200 System Workbench Library Developer (UNIX)
61400 61400 Test Synthesizer
61400 tsTSynVLOG Test Synthesizer
70000 AMS_environment Cadence(R) AMS designer environment
70001 Affirma_ams_simulator Cadence(R) AMS designer simulator
70001 Affirma_sim_analysis_env Cadence(R) AMS designer simulator
70110 365 Dracula(R) design rule checker
70110 Distributed_Dracula_Option Dracula(R) design rule checker
70110 DRAC2CORE Dracula(R) design rule checker
70110 DRAC3CORE Dracula(R) design rule checker
70110 DRAC3DRC Dracula(R) design rule checker
70110 DRACDIST Dracula(R) design rule checker
70110 DRACERC Dracula(R) design rule checker
70120 365 Dracula(R) layout vs. schematic verifier
70120 Distributed_Dracula_Option Dracula(R) layout vs. schematic
verifier
70120 DRAC2CORE Dracula(R) layout vs. schematic verifier
70120 DRAC3CORE Dracula(R) layout vs. schematic verifier
70120 DRAC3LVS Dracula(R) layout vs. schematic verifier
70120 DRACDIST Dracula(R) layout vs. schematic verifier
70120 DRACERC Dracula(R) layout vs. schematic verifier
70120 DRACLVS Dracula(R) layout vs. schematic verifier
70130 365 Dracula(R) parasitic extractor
70130 Distributed_Dracula_Option Dracula(R) parasitic extractor
70130 DRAC2CORE Dracula(R) parasitic extractor
70130 DRAC3CORE Dracula(R) parasitic extractor
70130 DRACDIST Dracula(R) parasitic extractor
70130 DRACLPE Dracula(R) parasitic extractor
70130 DRACPRE Dracula(R) parasitic extractor
71110 Assura_DV_design_rule_checker Diva(R) design rule checker
71110 plotVersa Diva(R) design rule checker
71120 Assura_DV_LVS_checker Diva(R) layout vs. schematic verifier
71120 plotVersa Diva(R) layout vs. schematic verifier
71130 Assura_DV_parasitic_extractor Diva(R) parasitic extractor
71130 plotVersa Diva(R) parasitic extractor
72110 Assura_DRC Assura(TM) design rule checker
72110 Assura_UI Assura(TM) design rule checker
72120 Assura_LVS Assura(TM) layout vs. schematic verifier
72120 Assura_UI Assura(TM) layout vs. schematic verifier
72130 Assura_RCX Assura(TM) parasitic extractor
72150 Assura_MP Assura(TM) multiprocessor option
80100 Envisia_Datapath_option Envisia(TM) Datapath Synthesis Option
80200 Envisia_LowPower_option Envisia(TM) Low Power Synthesis Option
AI2000 a2dxf CAD Interface Bundle
AI2000 actomd CAD Interface Bundle
AI2000 Allegro_CAD_Interface CAD Interface Bundle
AI2000 dxf2a CAD Interface Bundle
AI2000 IDF_Bi_Directional_Interface CAD Interface Bundle
AI2000 iges_electrical CAD Interface Bundle
AI2000 mdin CAD Interface Bundle
AI2000 mdout CAD Interface Bundle
AI2000 mdtoac CAD Interface Bundle
AI2000 ptc_in CAD Interface Bundle
AI2000 ptc_out CAD Interface Bundle
AI2000 sdrc_in CAD Interface Bundle
AI2000 sdrc_out CAD Interface Bundle
AI2100 Allegro_PCB_Interface PCB Interface Bundle
AI2100 visula_in PCB Interface Bundle
APT01 IC_edit Apprentice
APT01 IC_Inspector Apprentice
AR ABIT SPECCTRA(R) AutoRoute (UNIX)
AR allegro_non_partner SPECCTRA(R) AutoRoute (UNIX)
AR allegroprance SPECCTRA(R) AutoRoute (UNIX)
AR arouter SPECCTRA(R) AutoRoute (UNIX)
AR gloss SPECCTRA(R) AutoRoute (UNIX)
AR intrroute SPECCTRA(R) AutoRoute (UNIX)
AR placement SPECCTRA(R) AutoRoute (UNIX)
AR plotVersa SPECCTRA(R) AutoRoute (UNIX)
AR RouteBase SPECCTRA(R) AutoRoute (UNIX)
AR rt SPECCTRA(R) AutoRoute (UNIX)
AR swap SPECCTRA(R) AutoRoute (UNIX)
AR sx SPECCTRA(R) AutoRoute (UNIX)
AR tune SPECCTRA(R) AutoRoute (UNIX)
AR vgen SPECCTRA(R) AutoRoute (UNIX)
AR ViewBase SPECCTRA(R) AutoRoute (UNIX)
AS1200A AWB_SIMULATOR SPICE PLUS
AS1200A AWB_SPICEPLUS SPICE PLUS
AS22SP 32150 Spectre/Profile Add-on Special for AWB SPICE PLUS Users
(UNIX)
AS22SP 32500 Spectre/Profile Add-on Special for AWB SPICE PLUS Users
(UNIX)
AS22SP 32510 Spectre/Profile Add-on Special for AWB SPICE PLUS Users
(UNIX)
AS22SP AWB_BEHAVIOR Spectre/Profile Add-on Special for AWB SPICE PLUS
Users (UNIX)
AS22SP AWB_SIMULATOR Spectre/Profile Add-on Special for AWB SPICE PLUS
Users (UNIX)
AS22SP FUNCTION_LIB Spectre/Profile Add-on Special for AWB SPICE PLUS
Users (UNIX)
BG100 Ambit_BuildGates Ambit(R) BuildGates(R) synthesis
BG100 Envisia_Utility Ambit(R) BuildGates(R) synthesis
CDMATK Cierto_SPW_CDMA_Library Cadence(R) wideband CDMA library
CDMATKSIM SPW_LIB_CDMA_LIB Cierto(TM) CDMA library
CM00300 Celtic_Crosstalk_Analyzer CeltIC Crosstalk Analyzer for
Cell-based Designs
COMFLT Cierto_SPW_comm_lib_flt_pt Cadence(R) communication library -
floating point
COMTK Cierto_SPW_comm_library_fxp_pt Cadence(R) communication library
- fixed point
DESPRO BONES_DESIGNER_FRAMEWORK BONeS DESIGNER PRO
DESPRO BONES_FSM BONeS DESIGNER PRO
DESPRO BONES_INTERACTIVE_SIMULATION BONeS DESIGNER PRO
DESPRO BONES_PROJECT_EDITOR BONeS DESIGNER PRO
EF01 IC_editfast EditFast Option (requires Apprentice or better)
FDS SPW_FDS Cierto(TM) filter design system
FDS SPW_FMG Cierto(TM) filter design system
FE100 Encounter_C FE Ultra
FE100 Encounter_Wave_Viewer FE Ultra
FE100 Envisia_PKS FE Ultra
FE100 Envisia_Utility FE Ultra
FE100 FE_Ultra FE Ultra
FE150 Encounter_C Nanoroute Ultra
FE150 NanoRoute_Ultra Nanoroute Ultra
FET1100 ConceptHDL Concept HDL
FET1100 plotVersa Concept HDL
FET1101 concept Concept HDL (UNIX)
FET1200 Checkplus_Expert CheckPlus HDL
GRT01 IC_gcell_route Global Routing Option (requires Journeyman or
better)
GSMVE Cierto_SPW_GSM_VE Cadence(R) GSM verification environment
H299P partner Pillar Core
H299P pillar.db Pillar Core
H299P pillar.dpuxIn Pillar Core
H299P pillar.dpuxOut Pillar Core
H299P pillar.ge Pillar Core
H299P pillar.gui Pillar Core
H299P pillar.xl Pillar Core
H299P pillar.xlcm Pillar Core
H300 DPbase Physical DP III Core (CDS)
H300 HLDSbase Physical DP III Core (CDS)
H300 HLDSbaseC Physical DP III Core (CDS)
H345 DPsynopsys Envisia(TM) design planner interface to Synopsys
H415 DPbase Envisia(TM) physical design planner DSM (Pillar)
H415 DPbaseCell Envisia(TM) physical design planner DSM (Pillar)
H415 DPbaseGarray Envisia(TM) physical design planner DSM (Pillar)
H415 DPcctIcCraft Envisia(TM) physical design planner DSM (Pillar)
H415 DPcdsBE Envisia(TM) physical design planner DSM (Pillar)
H415 DPcdsC3 Envisia(TM) physical design planner DSM (Pillar)
H415 DPcdsCE Envisia(TM) physical design planner DSM (Pillar)
H415 DPcdsGE Envisia(TM) physical design planner DSM (Pillar)
H415 DPcdsPar Envisia(TM) physical design planner DSM (Pillar)
H415 DPcongest Envisia(TM) physical design planner DSM (Pillar)
H415 DPdelayCalc Envisia(TM) physical design planner DSM (Pillar)
H415 DPecoIpo Envisia(TM) physical design planner DSM (Pillar)
H415 DPextractRC Envisia(TM) physical design planner DSM (Pillar)
H415 DPfasnet Envisia(TM) physical design planner DSM (Pillar)
H415 DPgotc Envisia(TM) physical design planner DSM (Pillar)
H415 DPhyperPlaceCell Envisia(TM) physical design planner DSM (Pillar)
H415 DPhyperPlaceGarray Envisia(TM) physical design planner DSM
(Pillar)
H415 DPparasitic Envisia(TM) physical design planner DSM (Pillar)
H415 DPpearlLocked Envisia(TM) physical design planner DSM (Pillar)
H415 DPqplaceAB Envisia(TM) physical design planner DSM (Pillar)
H415 DPqplaceGA Envisia(TM) physical design planner DSM (Pillar)
H415 DPqplaceLocked Envisia(TM) physical design planner DSM (Pillar)
H415 DPrcExtract Envisia(TM) physical design planner DSM (Pillar)
H415 DPsdfConvPR Envisia(TM) physical design planner DSM (Pillar)
H415 DPsynopsys Envisia(TM) physical design planner DSM (Pillar)
H415 DPunivInterface Envisia(TM) physical design planner DSM (Pillar)
H415 HLDSbase Envisia(TM) physical design planner DSM (Pillar)
H415 HLDSbaseC Envisia(TM) physical design planner DSM (Pillar)
H415 partner Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.abstract Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.areaPdp Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.cdsIn Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.cdsOut Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.cellPdp Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.db Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.defIn Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.defOut Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.dpdev Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.dpuxIn Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.dpuxOut Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.edifIn Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.edifOut Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.gatePdp Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.gdsIn Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.gdsOut Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.ge Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.gui Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.ldexpand Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.lefIn Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.lefOut Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.pdp Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.verIn Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.verOut Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.vhdlIn Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.vhdlOut Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.xl Envisia(TM) physical design planner DSM (Pillar)
H415 pillar.xlcm Envisia(TM) physical design planner DSM (Pillar)
H475 DPbase Envisia(TM) physical design planner with signal integrity
features
H475 DPbaseCell Envisia(TM) physical design planner with signal
integrity features
H475 DPbaseGarray Envisia(TM) physical design planner with signal
integrity features
H475 DPcctIcCraft Envisia(TM) physical design planner with signal
integrity features
H475 DPcctIcCraft Envisia(TM) physical design planner with signal
integrity features
H475 DPcdsBE Envisia(TM) physical design planner with signal integrity
features
H475 DPcdsC3 Envisia(TM) physical design planner with signal integrity
features
H475 DPcdsCE Envisia(TM) physical design planner with signal integrity
features
H475 DPcdsGE Envisia(TM) physical design planner with signal integrity
features
H475 DPcdsPar Envisia(TM) physical design planner with signal
integrity features
H475 DPcongest Envisia(TM) physical design planner with signal
integrity features
H475 DPdelayCalc Envisia(TM) physical design planner with signal
integrity features
H475 DPecoIpo Envisia(TM) physical design planner with signal
integrity features
H475 DPextractRC Envisia(TM) physical design planner with signal
integrity features
H475 DPfasnet Envisia(TM) physical design planner with signal
integrity features
H475 DPgotc Envisia(TM) physical design planner with signal integrity
features
H475 DPhyperPlaceCell Envisia(TM) physical design planner with signal
integrity features
H475 DPhyperPlaceGarray Envisia(TM) physical design planner with
signal integrity features
H475 DPparasitic Envisia(TM) physical design planner with signal
integrity features
H475 DPpearlLocked Envisia(TM) physical design planner with signal
integrity features
H475 DPqplaceAB Envisia(TM) physical design planner with signal
integrity features
H475 DPqplaceAB Envisia(TM) physical design planner with signal
integrity features
H475 DPqplaceGA Envisia(TM) physical design planner with signal
integrity features
H475 DPqplaceGA Envisia(TM) physical design planner with signal
integrity features
H475 DPrcExtract Envisia(TM) physical design planner with signal
integrity features
H475 DPsdfConvPR Envisia(TM) physical design planner with signal
integrity features
H475 DPsdfConvPR Envisia(TM) physical design planner with signal
integrity features
H475 DPsynopsys Envisia(TM) physical design planner with signal
integrity features
H475 DPunivInterface Envisia(TM) physical design planner with signal
integrity features
H475 DPwplaceLocked Envisia(TM) physical design planner with signal
integrity features
H475 Envisia_DP_SI_design_planner Envisia(TM) physical design planner
with signal integrity features
H475 HLDSbase Envisia(TM) physical design planner with signal
integrity features
H475 HLDSbaseC Envisia(TM) physical design planner with signal
integrity features
H475 partner Envisia(TM) physical design planner with signal integrity
features
H475 pillar.abstract Envisia(TM) physical design planner with signal
integrity features
H475 pillar.areaPdp Envisia(TM) physical design planner with signal
integrity features
H475 pillar.cdsIn Envisia(TM) physical design planner with signal
integrity features
H475 pillar.cdsOut Envisia(TM) physical design planner with signal
integrity features
H475 pillar.cellPdp Envisia(TM) physical design planner with signal
integrity features
H475 pillar.db Envisia(TM) physical design planner with signal
integrity features
H475 pillar.defIn Envisia(TM) physical design planner with signal
integrity features
H475 pillar.defOut Envisia(TM) physical design planner with signal
integrity features
H475 pillar.dpdev Envisia(TM) physical design planner with signal
integrity features
H475 pillar.dpuxIn Envisia(TM) physical design planner with signal
integrity features
H475 pillar.dpuxOut Envisia(TM) physical design planner with signal
integrity features
H475 pillar.edifIn Envisia(TM) physical design planner with signal
integrity features
H475 pillar.edifOut Envisia(TM) physical design planner with signal
integrity features
H475 pillar.gatePdp Envisia(TM) physical design planner with signal
integrity features
H475 pillar.gdsIn Envisia(TM) physical design planner with signal
integrity features
H475 pillar.gdsOut Envisia(TM) physical design planner with signal
integrity features
H475 pillar.ge Envisia(TM) physical design planner with signal
integrity features
H475 pillar.gui Envisia(TM) physical design planner with signal
integrity features
H475 pillar.ldexpand Envisia(TM) physical design planner with signal
integrity features
H475 pillar.ldexpand Envisia(TM) physical design planner with signal
integrity features
H475 pillar.lefIn Envisia(TM) physical design planner with signal
integrity features
H475 pillar.lefOut Envisia(TM) physical design planner with signal
integrity features
H475 pillar.pdp Envisia(TM) physical design planner with signal
integrity features
H475 pillar.verIn Envisia(TM) physical design planner with signal
integrity features
H475 pillar.verOut Envisia(TM) physical design planner with signal
integrity features
H475 pillar.vhdlIn Envisia(TM) physical design planner with signal
integrity features
H475 pillar.vhdlOut Envisia(TM) physical design planner with signal
integrity features
H475 pillar.xl Envisia(TM) physical design planner with signal
integrity features
H475 pillar.xlcm Envisia(TM) physical design planner with signal
integrity features
H475 pillar.xlcm Envisia(TM) physical design planner with signal
integrity features
HDS SPW_LIB_HDS_ARC Cierto(TM) hardware design system - main
HDS SPW_LIB_HDS_ISL Cierto(TM) hardware design system - main
HDS SPW_LIB_HDS_LIB Cierto(TM) hardware design system - main
HDS SPW_LIB_HDS_MAIN Cierto(TM) hardware design system - main
HDS2000 Cierto_HW_design_sys_2000 Cadence(R) hardware design system
2000
HR200 partner Pillar DB/Lisp Development System
HR200 pillar.db Pillar DB/Lisp Development System
HR200 pillar.dbdev Pillar DB/Lisp Development System
HR200 pillar.dbperl Pillar DB/Lisp Development System
HR200 pillar.dpdev Pillar DB/Lisp Development System
HR200 pillar.ge Pillar DB/Lisp Development System
HR200 pillar.gui Pillar DB/Lisp Development System
HR200 pillar.vre Pillar DB/Lisp Development System
HR200 pillar.xl Pillar DB/Lisp Development System
HR200 pillar.xldev Pillar DB/Lisp Development System
IS136VE Cierto_SPW_IS136_VE Cadence(R) IS136 verification environment
JYM01 IC_autoroute Journeyman
JYM01 IC_edit Journeyman
JYM01 IC_Inspector Journeyman
LD01 LEFDEF_IF LEF/DEF Interface
LWB20 archiver Logic Workbench/SE SCALD (UNIX)
LWB20 Base_Digital_Body_Lib Logic Workbench/SE SCALD (UNIX)
LWB20 comp Logic Workbench/SE SCALD (UNIX)
LWB20 crefer Logic Workbench/SE SCALD (UNIX)
LWB20 expgen Logic Workbench/SE SCALD (UNIX)
LWB20 Extended_Digital_Body_Lib Logic Workbench/SE SCALD (UNIX)
LWB20 fethman Logic Workbench/SE SCALD (UNIX)
LWB20 fetsetup Logic Workbench/SE SCALD (UNIX)
LWB20 Framework Logic Workbench/SE SCALD (UNIX)
LWB20 gbom Logic Workbench/SE SCALD (UNIX)
LWB20 glib Logic Workbench/SE SCALD (UNIX)
LWB20 gphysdly Logic Workbench/SE SCALD (UNIX)
LWB20 gscald Logic Workbench/SE SCALD (UNIX)
LWB20 gspares Logic Workbench/SE SCALD (UNIX)
LWB20 LSE Logic Workbench/SE SCALD (UNIX)
LWB20 lwb Logic Workbench/SE SCALD (UNIX)
LWB20 OpenModeler Logic Workbench/SE SCALD (UNIX)
LWB20 OpenModeler_SFI Logic Workbench/SE SCALD (UNIX)
LWB20 OpenModeler_SWIFT Logic Workbench/SE SCALD (UNIX)
LWB20 OpenWaves Logic Workbench/SE SCALD (UNIX)
LWB20 packager Logic Workbench/SE SCALD (UNIX)
LWB20 pcomp Logic Workbench/SE SCALD (UNIX)
LWB20 plotVersa Logic Workbench/SE SCALD (UNIX)
LWB20 realchiplm Logic Workbench/SE SCALD (UNIX)
LWB20 tscr.ex Logic Workbench/SE SCALD (UNIX)
LWB20 UET Logic Workbench/SE SCALD (UNIX)
LWB20 VHDLLink Logic Workbench/SE SCALD (UNIX)
LWB20 vloglink Logic Workbench/SE SCALD (UNIX)
MNT BRDST_IF SPECCTRA(R)-BoardStation Interface (Windows)
MST01 IC_autoroute Master
MST01 IC_edit Master
MST01 IC_hsrules Master
MST01 IC_Inspector Master
NCSPW Cierto_SPW_link_to_NC_sim Cadence(R) signal processing
worksystem link to NC simulators
PCSCDMAVE Cierto_SPW_pcscdma_VE Cadence(R) PCS CDMA verification
environment
PE2300 allegro_non_partner SPECCTRAQuest Expert
PE2300 allegroprance SPECCTRAQuest Expert
PE2300 BoardQuest_Designer SPECCTRAQuest Expert
PE2300 BoardQuest_Team SPECCTRAQuest Expert
PE2300 EditBase_ALL SPECCTRAQuest Expert
PE2300 EditFST_ALL SPECCTRAQuest Expert
PE2300 Framework SPECCTRAQuest Expert
PE2300 intrsignoise SPECCTRAQuest Expert
PE2300 plotVersa SPECCTRAQuest Expert
PE2300 PPRoute_ALL SPECCTRAQuest Expert
PE2300 rt SPECCTRAQuest Expert
PE2300 signoise SPECCTRAQuest Expert
PE2300 SigNoise_Float SPECCTRAQuest Expert
PE2300 SigNoiseCS SPECCTRAQuest Expert
PE2300 SigNoiseEngineer SPECCTRAQuest Expert
PE2300 SPECCTRAQuest_Planner SPECCTRAQuest Expert
PE2300 SPECCTRAQuest_signal_expert SPECCTRAQuest Expert
PE2300 sx SPECCTRAQuest Expert
PE2300 tune SPECCTRAQuest Expert
PE2300 vgen SPECCTRAQuest Expert
PE2300 ViewBase_ALL SPECCTRAQuest Expert
PE2600 EMCdisplay EMControl
PE2600 EMControl EMControl
PE2600 EMControl_Float EMControl
PO1100 Capture Capture
PO1110 CaptureCIS Capture CIS
PO1310 PSpice Pspice
PO1320 PSpiceAD Pspice A/D
PO1340 PSpiceAA Pspice Advanced Analysis Option
PO1400 LayoutEE Layout Eng Ed
PO1410 Layout Layout
PO1420 LayoutPlus Layout Plus
PRT01 IC_power_route Power Routing Option (requires Journeyman or
better)
PS2000 Allegro_Viewer_Plus Concept(R) HDL studio
PS2000 Base_Verilog_Lib Concept(R) HDL studio
PS2000 Concept_HDL_studio Concept(R) HDL studio
PS2000 Extended_Verilog_Lib Concept(R) HDL studio
PS2000 plotVersa Concept(R) HDL studio
PS2100 Concept_HDL_rules_checker Concept(R) HDL rules checker option
PS3000 Allegro_studio PCB design studio with Concept(R) HDL
PS3000 Base_Verilog_Lib PCB design studio with Concept(R) HDL
PS3000 Extended_Verilog_Lib PCB design studio with Concept(R) HDL
PS3000 PCB_design_studio PCB design studio with Concept(R) HDL
PS3000 plotVersa PCB design studio with Concept(R) HDL
PS3000 SPECCTRA_PCB PCB design studio with Concept(R) HDL
PS3100 Allegro_performance Allegro(R) performance option
PS3100 plotVersa Allegro(R) performance option
PS3600 RouteMVIA_ALL SPECCTRA(R) performance option
PS3600 SPECCTRA_performance SPECCTRA(R) performance option
PX3000 Allegro_Viewer_Plus Concept(R) HDL expert
PX3000 Base_Verilog_Lib Concept(R) HDL expert
PX3000 Concept_HDL_expert Concept(R) HDL expert
PX3000 Extended_Verilog_Lib Concept(R) HDL expert
PX3000 plotVersa Concept(R) HDL expert
PX3400 SQ_Digital_Logic_SI_Lib digital logic SI library
PX3500 Allegro_studio PCB librarian expert
PX3500 Base_Verilog_Lib PCB librarian expert
PX3500 Extended_Verilog_Lib PCB librarian expert
PX3500 PCB_librarian_expert PCB librarian expert
PX3500 plotVersa PCB librarian expert
PX3700 Allegro_design_expert PCB design expert with Concept HDL
PX3700 PCB_design_expert PCB design expert with Concept HDL
PX3700 PlaceBase_ALL PCB design expert with Concept HDL
PX3700 plotVersa PCB design expert with Concept HDL
PX3700 RouteMVIA_ALL PCB design expert with Concept HDL
PX3700 SPECCTRA_expert PCB design expert with Concept HDL
PX3800 PlaceBase_ALL SPECCTRA(R) expert system
PX3800 RouteMVIA_ALL SPECCTRA(R) expert system
PX3800 SPECCTRA_expert_system SPECCTRA(R) expert system
PX3900 Allegro_designer_suite PCB designer with Concept HDL
PX3900 PCB_designer PCB designer with Concept HDL
PX3900 PlaceBase_ALL PCB designer with Concept HDL
PX3900 plotVersa PCB designer with Concept HDL
PX3900 RouteMVIA_ALL PCB designer with Concept HDL
PX3900 SPECCTRA_designer PCB designer with Concept HDL
PX4000 adv_package_engineer_expert advanced package engineer expert
PX4000 advanced_package_designer advanced package engineer expert
PX4000 PlaceBase_ALL advanced package engineer expert
PX4000 plotVersa advanced package engineer expert
PX4000 RouteMVIA_ALL advanced package engineer expert
PX4000 SPECCTRA_expert advanced package engineer expert
PX4000 SPECCTRAQuest advanced package engineer expert
PX4000 SPECCTRAQuest_signal_expert advanced package engineer expert
PX4100 adv_package_designer_expert Advanced package designer expert
PX4100 advanced_package_designer Advanced package designer expert
PX4100 PlaceBase_ALL Advanced package designer expert
PX4100 plotVersa Advanced package designer expert
PX4100 RouteMVIA_ALL Advanced package designer expert
PX4100 SPECCTRA_expert Advanced package designer expert
RA100 Multithread_Route_Option Multithreaded Router Option
SIG01 signalscan Cadence(R) Signalscan
SIG01 signalscan-compress Cadence(R) Signalscan
SIG02 comparescan Cadence(R) Signalscan-TX
SIG02 signalscan Cadence(R) Signalscan-TX
SIG02 signalscan-compress Cadence(R) Signalscan-TX
SIG02 signalscan-pro Cadence(R) Signalscan-TX
SIG02 signalscan-transaction Cadence(R) Signalscan-TX
SP2000 RB_6SUPUC_ALL SPECCTRA PCB Autorouter
SP2000 VB_6SUPUC_ALL SPECCTRA PCB Autorouter
SPR001 22810 Silicon Ensemble(TM) PKS optimization place-and-route
SPR001 Clock_Tree_Generation Silicon Ensemble(TM) PKS optimization
place-and-route
SPR001 Envisia_PKS Silicon Ensemble(TM) PKS optimization
place-and-route
SPR001 Envisia_SE_SI_place_route Silicon Ensemble(TM) PKS optimization
place-and-route
SPR001 Envisia_SE_ultra_place_route Silicon Ensemble(TM) PKS
optimization place-and-route
SPR001 Envisia_Utility Silicon Ensemble(TM) PKS optimization
place-and-route
SPR001 Silicon_Ensemble Silicon Ensemble(TM) PKS optimization
place-and-route
SPR001 Silicon_Ensemble_DSM Silicon Ensemble(TM) PKS optimization
place-and-route
SPW SPW_BDE Cierto(TM) signal processing worksystem
SPW SPW_FMG Cierto(TM) signal processing worksystem
SPW SPW_FMG Cierto(TM) signal processing worksystem
SPW SPW_SIGCALC Cierto(TM) signal processing worksystem
SPW SPW_SIM Cierto(TM) signal processing worksystem
SPW SPW_SIM_UI Cierto(TM) signal processing worksystem
SPW2000 Cierto_signal_proc_wrksys_2000 Cadence(R) signal processing
worksystem 2000
SPWDPL Cierto_SPW_link_to_Ambit_BG SPW/HDS link to Ambit BG DP
optimization
SPWLSF SPW_LSF_Link SPW LSF Link
SPWPRO SPW_BDE Cierto(TM) signal processing work station
SPWPRO SPW_CGS_ANY Cierto(TM) signal processing work station
SPWPRO SPW_CGS_STANDARD_C Cierto(TM) signal processing work station
SPWPRO SPW_DATA_MANAGEMENT Cierto(TM) signal processing work station
SPWPRO SPW_FMG Cierto(TM) signal processing work station
SPWPRO SPW_FSM Cierto(TM) signal processing work station
SPWPRO SPW_LIB_ISL Cierto(TM) signal processing work station
SPWPRO SPW_SIGCALC Cierto(TM) signal processing work station
SPWPRO SPW_SIM Cierto(TM) signal processing work station
SPWPRO SPW_SIM_UI Cierto(TM) signal processing work station
TW02 tw01 Cadence(R) team design project adminsitrator
TW02 tw02 Cadence(R) team design project adminsitrator
V29 Affirma_model_checker FormalCheck(R) model checker
V29 Affirma_sim_analysis_env FormalCheck(R) model checker
V29 Model_Check_Analysis FormalCheck(R) model checker
VCCACT Cierto_SPW_model_manager Cadence(R) virtual component co-design
architect bundle
VCCACT SDT_MODEL_MANAGER Cadence(R) virtual component co-design
architect bundle
VCCACT VCC_Editors Cadence(R) virtual component co-design architect
bundle
VCCACT VCC_links_to_implementation Cadence(R) virtual component
co-design architect bundle
VCCACT VCC_Simulators Cadence(R) virtual component co-design architect
bundle
VCCACT VCC_SW_Estimator Cadence(R) virtual component co-design
architect bundle
VT1000 actomd PCB Librarian
VT1000 Allegro_Librarian PCB Librarian
VT1000 allegro_non_partner PCB Librarian
VT1000 allegro_symbol PCB Librarian
VT1000 cals_out PCB Librarian
VT1000 cbds_in PCB Librarian
VT1000 cdxe_in PCB Librarian
VT1000 cvtomd PCB Librarian
VT1000 Framework PCB Librarian
VT1000 hp3070 PCB Librarian
VT1000 ipc_in PCB Librarian
VT1000 ipc_out PCB Librarian
VT1000 mdin PCB Librarian
VT1000 mdout PCB Librarian
VT1000 mdtoac PCB Librarian
VT1000 mdtocv PCB Librarian
VT1000 multiwire PCB Librarian
VT1000 pcb_prep PCB Librarian
VT1000 PE_Librarian PCB Librarian
VT1000 plotVersa PCB Librarian
VT1000 quanticout PCB Librarian
VT2000 Allegro_PCB Allegro PCB
VT2000 Framework Allegro PCB
VT2000 plotVersa Allegro PCB
VT2100 actomd Allegro Designer
VT2100 Allegro_Designer Allegro Designer
VT2100 allegro_dfa Allegro Designer
VT2100 allegro_dfa_att Allegro Designer
VT2100 allegro_non_partner Allegro Designer
VT2100 allegro_symbol Allegro Designer
VT2100 cals_out Allegro Designer
VT2100 cbds_in Allegro Designer
VT2100 cdxe_in Allegro Designer
VT2100 cvtomd Allegro Designer
VT2100 Framework Allegro Designer
VT2100 hp3070 Allegro Designer
VT2100 intrgloss Allegro Designer
VT2100 intrroute Allegro Designer
VT2100 ipc_in Allegro Designer
VT2100 ipc_out Allegro Designer
VT2100 IPlaceBase_ALL Allegro Designer
VT2100 mdin Allegro Designer
VT2100 mdout Allegro Designer
VT2100 mdtoac Allegro Designer
VT2100 mdtocv Allegro Designer
VT2100 multiwire Allegro Designer
VT2100 pcb_interactive Allegro Designer
VT2100 PlaceBase_ALL Allegro Designer
VT2100 plotVersa Allegro Designer
VT2100 quanticout Allegro Designer
VT2100 ViewBase_ALL Allegro Designer
VT2200 actomd Allegro Expert
VT2200 allegro_dfa Allegro Expert
VT2200 allegro_dfa_att Allegro Expert
VT2200 Allegro_Expert Allegro Expert
VT2200 allegro_non_partner Allegro Expert
VT2200 allegro_symbol Allegro Expert
VT2200 arouter Allegro Expert
VT2200 cals_out Allegro Expert
VT2200 cbds_in Allegro Expert
VT2200 cdxe_in Allegro Expert
VT2200 cvtomd Allegro Expert
VT2200 EditBase_ALL Allegro Expert
VT2200 EditFST_ALL Allegro Expert
VT2200 Framework Allegro Expert
VT2200 gloss Allegro Expert
VT2200 hp3070 Allegro Expert
VT2200 intrgloss Allegro Expert
VT2200 intrroute Allegro Expert
VT2200 intrsignoise Allegro Expert
VT2200 ipc_in Allegro Expert
VT2200 ipc_out Allegro Expert
VT2200 IPlaceBase_ALL Allegro Expert
VT2200 mdin Allegro Expert
VT2200 mdout Allegro Expert
VT2200 mdtoac Allegro Expert
VT2200 mdtocv Allegro Expert
VT2200 multiwire Allegro Expert
VT2200 pcb_editor Allegro Expert
VT2200 PlaceBase_ALL Allegro Expert
VT2200 placement Allegro Expert
VT2200 plotVersa Allegro Expert
VT2200 PPRoute_ALL Allegro Expert
VT2200 quanticout Allegro Expert
VT2200 signoise Allegro Expert
VT2200 SigNoiseEngineer Allegro Expert
VT2200 swap Allegro Expert
VT2200 ViewBase_ALL Allegro Expert
VT2300 actomd Advanced Package Designer
VT2300 Advanced_Package_Designer Advanced Package Designer
VT2300 allegro_non_partner Advanced Package Designer
VT2300 allegro_symbol Advanced Package Designer
VT2300 APD Advanced Package Designer
VT2300 cals_out Advanced Package Designer
VT2300 cbds_in Advanced Package Designer
VT2300 cdxe_in Advanced Package Designer
VT2300 cvtomd Advanced Package Designer
VT2300 EditBase_ALL Advanced Package Designer
VT2300 EditFST_ALL Advanced Package Designer
VT2300 Framework Advanced Package Designer
VT2300 hp3070 Advanced Package Designer
VT2300 intrgloss Advanced Package Designer
VT2300 ipc_in Advanced Package Designer
VT2300 ipc_out Advanced Package Designer
VT2300 IPlaceBase_ALL Advanced Package Designer
VT2300 mdin Advanced Package Designer
VT2300 mdout Advanced Package Designer
VT2300 mdtoac Advanced Package Designer
VT2300 mdtocv Advanced Package Designer
VT2300 multiwire Advanced Package Designer
VT2300 PlaceBase_ALL Advanced Package Designer
VT2300 plotVersa Advanced Package Designer
VT2300 PPRoute_ALL Advanced Package Designer
VT2300 quanticout Advanced Package Designer
VT2300 ViewBase_ALL Advanced Package Designer
WLAN Cierto_Wireless_LAN_Library Cadence(R) wireless local area
networks library
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Erik