layout

Hi all
1- should we put the PPLUS, NwellIn, NPLUS and so on for all the
transistors in the layout of a circuit? please tell your reason.
2- is it bad idea to set m=2 for resistor in the layout and compact
the circuit rather than set to 1?

Regards

 

ECS.MSc.SOC wrote, on 12/15/10 03:00:

Please do some research before asking questions like this in a forum. Your
questions are very open ended and suggest that you have not tried reading any
books or done any searching first. You may also want to ask your supervisor (I'm
guessing you're a university student). Without doing basic research first,
there's a high chance your questions will get ignored.

The transistors (you didn't say what type, but one would assume MOS) won't be
transistors unless you have the appropriate implant (e.g. PPLUS, NPLUS) over
them. And P transistors will normally need to be in an nwell. So this is a bit
of an odd question.

The second question depends on whether you have any matching requirements in the
design. Most IC design depends on matching devices rather than absolute values,
so you tend to design in terms of unit multiples of component sizes in order to
get matching and ratios between devices.

Regards,

Andrew.

 

Hi Andrew,
I am new to cadence. I want to save gm,gds...i.e the operating points
for the transistors while doing dc sweep. I read your procedure of
including a .scs file for doing this. Is there any simpler method for
this in IC6.1?

 

Jagadish wrote, on 12/16/10 03:00:

Please don't reply to threads on completely new subjects - one was on layout,
and the other on saving operating point data! Makes for rather confusing reading...

Anyway, no, there is no simpler way (yet) to do this in IC6.1.

Regards,

Andrew.