latch up failure

Dear All

I need some help to understand more about latch up failure.
Usually, latch up failure happens are due to improper layout of design
OR due to process issue?

I heard that often latch up failure happens in IO mos. What are they
for? Why it is often the case latch up happens at IO mos? Is the W/L
bigger than normal logic mos or some other reason?

If anyone has any good reference on this topic, kindly share with me.

Thank you for your help.

best rgds
Jason

 

A search on google on "latch-up CMOS" give quite informative hits at
the top.
http://www.fairchildsemi.com/an/AN/AN-600.pdf and
http://www.fairchildsemi.com/an/AN/AN-339.pdf

are application notes from the gory days when latch-up was more a
problem than today. I didn't have time to read them, but I verified
that the important cross-section diagram that explains _where_ latch-up
happens and not only _why_ it happens. I did once have the pleasure to
experience non-destructive latch-up in the lab. Funny experience.

 

The most common cause of latch-up is you do not have well or substrate
taps near enough to the device which is failing.

As it was explained to me, the resistance from the power rail to the
material under the device is too high and prevents sufficient charge
forming under the device. Add more taps closer to the device and it is
fixed.

I'm just a software guy with a little IC design experience, so I'm sure
they gave me the idiots guide explanation. There is no doubt a very
specific explanation based on semiconductor physics and relative P-N
junction potentials.