Integration between Cadence design flows and foundries' design kits

Discussion in 'Cadence' started by spectrallypure, Dec 31, 2005.

  1. Dear all, I am new to the Cadence design flow. A few months ago I
    installed and setup myself the following:

    1. Solaris 10 (running on a SUN sparc platform)
    2. Cadence IC package v5.0.33, acquired through EUROPRACTICE -no
    Sourcelink support! :(
    3. AMS HitKit v3.60B (for creating schematics I use the "ams_cds"
    script with the following options: "ams_cds -techfile c35b4 -mode fb").

    Al these software seems to be working just fine (no licensing problems
    or the like), and so far I have completed a full-custom analog design
    at the schematic entry level using Virtuoso Composer and the Analog
    Design Environment for simulation. But before proceeding into the
    layout and further stages of the design flow, I need to solve the
    following problems (please note that I am only talking about full
    custom analog design - I am not planning to use synthesis tools,
    standard cells, automated place and route, etc.; whose mastery I reckon
    might be rather tough!):

    1. I have no idea about how exactly the integration between the Cadence
    tools and the design kit is performed. At the schematic entry level, I
    though that this was accomplished by simply using the appropriate MOS
    model files for the instances in the schematic, but I was unable to
    find information (i.e. a guide) about which components are included in
    the design kit and how they are associated with the models. I even had
    to proceed by trial and error to find the most basic active components
    (nmos4 and pmos4), but I am sure there should be a resource somewhere
    explaining the contents of the libraries in the design kit and the
    models associated with them.

    2. I don't understand what the different "modes" of the design kit
    mean. The AMS hitkit documentation only mentions that the following
    modes exist (but it doesn't explain exactly what the differences
    between them are, the Cadence tools they interact with, when to use
    which, or in which order they should be used!):

    fb (for front end back end), ms (for mixed-signal), msfb (for mixed
    signal front-back), ds (digital schematic), ly (for layout), lyp (for
    layout plus), ca (for cellEnsemble/Preview).

    For instance, after successfully simulating my schematic, which mode of
    the design kit should I use in order to create the layout (full
    custom)? ¿ly? ¿lyp? ¿what are the differences between these two?.

    3. My final goal is to produce GDSII files ready to be sent to the
    foundry for fabrication, but I am unaware of the exact steps one should
    follow for this purpose within the Cadence design flow (there exist so
    many tools and for so many different cases that I have gotten really
    confused!) What I need to known are the detailed steps that should be
    followed in order to go all the way from schematic level entry down to
    the GDSII files, for a real implementation.

    4. Is there any official chart for the different design flows that can
    be implemented with Cadence? Also, is there a formal definition of what
    exactly is meant by "front end", "back end" and "front-back", and what
    steps of a design flow they comprise?.

    Thanks so much for any help regarding these topics.
    Best regards.
     
    spectrallypure, Dec 31, 2005
    #1
  2. The mode "fb" allows you to run the tools from the front-end design flow
    and the tools from the backend design flow.

    Front-end tools are the ones that deal with schematics, netlists,
    simulation. No layout information is needed.
    For digital design flows the logic synthesis is in this part of
    the flow.

    Backend tools are dealing with all information related to layout.
    Layout synthesis, layout edition, placement, routing, DRC, extraction,
    parasitics simulation, layout finishing, etc ...

    You should ask your design-kit provider to give you access to a
    training on the design-kit.
    If you are in Europe, there will be one planned in March
    15th and 16th in Sweden :
    http://www.csee.ltu.se/index.php?subject=asic

    Regards,
    ==============
    Kholdoun TORKI
    http://cmp.imag.fr
    ==============
     
    Kholdoun TORKI, Jan 2, 2006
    #2
  3. Dear Kholdoun,

    Thanks a lot for your response. Unluckily, I live in South America, so
    it is always a little difficult for us to attend live seminars on EDA
    tools and the like. Also, since we get the Cadence suite from
    EUROPRACTICE, we have a rather limited support plan. Nevertheless, I
    will try to contact them to see if they can help by providing some
    information.

    Thanks again for your appreciated help!

    PS. Would there be in the web any documentation about Cadence Design
    flows that could help?
     
    spectrallypure, Jan 3, 2006
    #3
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