inherited connections & diva parasitics

We are using inherited connections in our schematics for

power
gnd
substrate

A sample spectre netlist for a subckt is shown below. When we run
diva parasitic rc extraction and netlist we get a netlist that does
not connect up the inherited connections. This netlist is also
included. Notice that the subckt call for the extracted version does
not have the inherited connections. Has anyone been able to get
this to work?

subckt AnalogMux_21 D0 D1 SD Z inh_power inh_gnd inh_substrate inh_vdd
I2 (inh_gnd inh_substrate) subc l=4u w=2u dtemp=0
T106 (Z n11 D0 inh_substrate) nfet nf=1 m=1 w=2.4u l=500n
ad=3.21e-12 \
as=3.21e-12 pd=7.35u ps=7.35u nrs=0.317778 nrd=0.317778
dtemp=0 \
gcon=1 nqsmod=0
T100 (n11 SD inh_gnd inh_substrate) nfet nf=1 m=1 w=1.3u l=500n \
ad=2.07e-12 as=2.07e-12 pd=5.75u ps=5.75u nrs=0.621739 \
nrd=0.621739 dtemp=0 gcon=1 nqsmod=0
T99 (Z SD D1 inh_substrate) nfet nf=1 m=1 w=2.4u l=500n
ad=3.21e-12 \
as=3.21e-12 pd=7.35u ps=7.35u nrs=0.317778 nrd=0.317778
dtemp=0 \
gcon=1 nqsmod=0
T104 (Z SD D0 inh_power) pfet nf=1 m=1 w=4.8u l=500n ad=6.63e-12 \
as=6.63e-12 pd=12.15u ps=12.15u nrs=0.153763 nrd=0.153763
dtemp=0 \
gcon=1 nqsmod=0
T102 (n11 SD inh_vdd inh_power) pfet nf=1 m=1 w=2.5u l=500n \
ad=3.35e-12 as=3.35e-12 pd=7.55u ps=7.55u nrs=0.304255 \
nrd=0.304255 dtemp=0 gcon=1 nqsmod=0
T101 (Z n11 D1 inh_power) pfet nf=1 m=1 w=4.8u l=500n ad=6.63e-12
\
as=6.63e-12 pd=12.15u ps=12.15u nrs=0.153763 nrd=0.153763
dtemp=0 \
gcon=1 nqsmod=0
ends AnalogMux_21


subckt AnalogMux_21_extracted_c D0 D1 SD Z
\+34 (_net0 _net1) pcapnx area=4.35e-12 perim=1.57e-05
\+33 (SD _net1) pcapnx area=6.325e-13 perim=3.4e-06
\+32 (_net2 _net1) pcapnwx area=2.106e-10 perim=1.3e-05
\+31 (_net0 _14) pcapc c=1.9275e-17
\+30 (Z _14) pcapc c=3.61557e-17
\+29 (Z _net0) pcapc c=7.06823e-18
\+28 (_net2 _14) pcapc c=1.21961e-15
\+27 (_net2 Z) pcapc c=1.11002e-16
\+26 (_net1 _14) pcapc c=9.18075e-16
\+25 (_net1 _net0) pcapc c=1.81019e-15
\+24 (_net1 Z) pcapc c=2.561e-16
\+23 (D1 _14) pcapc c=1.59733e-17
\+22 (D1 _net0) pcapc c=7.06823e-18
\+21 (D1 Z) pcapc c=2.5795e-16
\+20 (D1 _net2) pcapc c=1.55187e-16
\+19 (D1 _net1) pcapc c=4.0739e-16
\+18 (D0 _14) pcapc c=2.78874e-16
\+17 (D0 _net0) pcapc c=7.06823e-18
\+16 (D0 Z) pcapc c=2.56182e-16
\+15 (D0 _net2) pcapc c=1.11002e-16
\+14 (D0 _net1) pcapc c=2.561e-16
\+13 (SD _14) pcapc c=3.49018e-16
\+12 (SD _net0) pcapc c=2.93434e-18
\+11 (SD Z) pcapc c=1.40261e-16
\+10 (SD _net2) pcapc c=4.39299e-16
\+9 (SD _net1) pcapc c=2.29198e-15
\+8 (SD D1) pcapc c=3.60479e-17
\+7 (SD D0) pcapc c=1.08549e-16
\+6 (_net0 _net1) subc l=1.14e-05 w=6e-07 dtemp=0
\+5 (_net2 SD _14 _net2) pfet nf=1 m=1 w=2.5e-06 l=5e-07 \
ad=1.03763e-11 as=3.34875e-12 pd=2.835e-05 ps=7.55e-06 \
nrs=0.304255 nrd=0.304255 dtemp=0 gcon=1 nqsmod=0
\+4 (D0 SD Z _net2) pfet nf=1 m=1 w=4.8e-06 l=5e-07 ad=6.62625e-12
\
as=3.72e-12 pd=1.215e-05 ps=6.25e-06 nrs=0.153763 nrd=0.153763
\
dtemp=0 gcon=1 nqsmod=0
\+3 (Z _14 D1 _net2) pfet nf=1 m=1 w=4.8e-06 l=5e-07 ad=3.72e-12 \
as=6.62625e-12 pd=6.25e-06 ps=1.215e-05 nrs=0.153763
nrd=0.153763 \
dtemp=0 gcon=1 nqsmod=0
\+2 (_net0 SD _14 _net1) nfet nf=1 m=1 w=1.3e-06 l=5e-07 \
ad=5.81625e-12 as=1.63875e-12 pd=1.825e-05 ps=5.15e-06 \
nrs=0.621739 nrd=0.621739 dtemp=0 gcon=1 nqsmod=0
\+1 (D0 _14 Z _net1) nfet nf=1 m=1 w=2.4e-06 l=5e-07
ad=3.20625e-12 \
as=1.8e-12 pd=7.35e-06 ps=3.85e-06 nrs=0.317778 nrd=0.317778 \
dtemp=0 gcon=1 nqsmod=0
\+0 (Z SD D1 _net1) nfet nf=1 m=1 w=2.4e-06 l=5e-07 ad=1.8e-12 \
as=3.20625e-12 pd=3.85e-06 ps=7.35e-06 nrs=0.317778
nrd=0.317778 \
dtemp=0 gcon=1 nqsmod=0
ends AnalogMux_21_extracted_c

 

Start be making sure the layout you are extracting from has pins. From
your netlist, you can see there are NO pins for power, gnd, substrate,
and vdd. Then make sure the pins have the correct inherited expressions.
The extractor cannot create inherited expressions out of thin air, you
have to provide them in the layout.