including CDL netlist component for Assura LVS

Hello,

I couldn't find the solution of my problem so I hope to find an advice
here.

The problem is that Assura doesn't recognize the device described in
the CDL netlist attached to auLvs cellView.

I have a CDL netlist of some block (EEPROM) and a layout of this
block.

For this block I've created the auLvs cellview (derived from the
symbol) and added the user property CDL_NETLIST_FILE =
<netlist_file_name.cdl>.

CDL netlist file has been copied to auLvs directory.
Also I edited the syminfo sections of the CDF parameters for the auLvs
cellview:

netlistProcedure = ansLvsCompPrim
componentName = <Name_of_my_cell>
termOrder = <list_of_all_terminals>
namePrefix = "X

This block has been inserted in top schematic.

Then, when I try to run top LVS with Assura 3.2, it can't find the
information about my device in Schematic, i.e., can't read the CDL
netlist.

Following error messages in Assura LVS log file:

...............
*WARNING* Device information not found for cell EEPROM in library
DIGMEM.
...............
*ERROR* Device 'EEPROM(Generic)' on Schematic is unbound to any Layout
device.
.............

What is the correct procedure of binding the CDL netlist to auLvs
cellview?

When I use auCdl view of this cell to export the CDL-netlist of whole
schematic for DRACULA LVS, it works perfectly!
But I'd like to have a possibility to use Assura LVS as well.
Could you help me with this issue?

 

I dont believe that Assura has the ability to run both DFII and CDL at
the same time yet. There are various supported combinations such
as verilog and CDL. As a workaround you can run cdltovld (think) and
then access both netlists but Ive never tried it because there are
easier ways. Im guessing that you dont have a schematic....is that
right? You can run Assura with a CDL netlist either by dumping the
entire design or by adding it in the "include file" section if you
dont have the schematic. Also you can import the CDL and create a
schematic.

Rick

 

rick wrote, on 06/22/10 19:43:

Rick,

Yes Assura does support this (and has for quite some time). On the LVS form, if
the Schematic Design Source is "DFII", you can hit the "Netlisting Options"
form, and at the bottom you can add additional CDL, Verilog and SPICE netlists
to augment your schematic design.

Regards,

Andrew.