How to make a cap like a cap in pdk?

Discussion in 'Cadence' started by YUAN Shuai, Mar 23, 2011.

  1. YUAN Shuai

    YUAN Shuai Guest

    I would like to make my own M1-M2 plate capacitor that could be
    parameterized.
    Cadence has a sample pcell example of making parameterized layout.
    however, I also want to make symbols for the cap and the symbol will
    be used in the schematic. And some questions are:
    1. how to enable LVS of the symbol in schematic and the pcell layout?
    2. how to build the model of the layout pcell so the
    simulator(Spectre) can link the symbol with my own cap model?

    Thanks!
     
    YUAN Shuai, Mar 23, 2011
    #1
  2. YUAN Shuai

    Andrew Beckett Guest

    YUAN Shuai wrote, on 03/23/11 12:51:
    You might want to take a look at
    http://support.cadence.com/wps/mypo...=cic_pdks/PRD_Methodology_Guide_version_2.pdf

    Regards,

    Andrew.
     
    Andrew Beckett, Apr 1, 2011
    #2
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