How to determine IO cell placement for a mixed signal system on a chip?

What do real ic designers use to place I/O cells & pads in an SOC?

For my ic basics class, I have to write a ten-page thousand-word paper
on the complete cmos ic design process flow for a select type of 180nm
chip given industry libraries (tsmc is ok. Instead of RF, custom, or
digital ICs, I chose to write on the SOC (assume 50:50 low-speed
analog & 500 Mhz digital on top with a token 802.11 interface for
completeness).

I don't have to mention specific eda tools but my professor says this
cadence newsgroup is one of the best resoures outside the university
for real world answers (not theoretical) because cadence has all three
ic domains locked up (he says there's cadence, and all the rest). So
I'm here.

So far...

I've got most of the basic flow written down except for how I/O shows
up (either in-line, staggered, flip-chip, or system in package). But
I'm stumped on the IO placement (both the ESD pad and the bond pad
with filet) process. Everything I have located (which isn't much)
simply says to "read in a preexisting I/O placement file".

This makes no sense to me unless the placement is always a given
finality.
Certainly the I/O esd & pad placement & net naming labels *can* be
read in, but, I can't believe *everyone* *always* punts on this task
by reading in a predefined file which places the io cells, pads, and
filets and then names each of the connecting nets on the SOC
accordingly.

What if a predefined I/O placement is not optimal for a given SOC
design?

I'm stumped...

In the real world, how do we decide where to place I/O pads on a mixed
analog and digital system on a chip?

I await your response,
Donna B.