How to design an even/odd parity generator in Cadence?

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Hi everyone,
I am trying to design a parity generator in Cadence that can handle both even and odd parity. I’m a bit unsure about how to approach this in terms of schematic design and simulation.

Could someone please guide me on:

• How to implement the logic for both even and odd parity?
  
  
• How to configure this in Cadence (e.g. using schematic, Verilog, or both)?
  
  
• Any best practices or examples for testing the design in simulation?
  

Any advice, example circuits, or references would be greatly appreciated.
Thanks in advance!