HELP ME! Just one open remaining on chip after CONNECT RING in Silicon Ensemble?

Discussion in 'Cadence' started by walala, Oct 7, 2003.

  1. walala

    walala Guest

    Dear all,

    I guess this is a small problem, but how to solve it? I struggled for a few
    hours, but did not get through:

    I have 1 open remained after CONNECT RING command, before I do WROUTE. Is
    there any search and repair kind of function for CONNECT RING? What can I do
    to eliminate this only remaining OPEN? Is it helpful to put a
    stripe?(Currently I am not doing any stripe, after seeing your suggestions).
    Is there a incremental/search-repair "PLACE", maybe redo "PLACE" will help?

    I am a little sure that if I put "filler cells", maybe this 1 open will
    gone. But I don't want to put "filler cells" because since the circuit is
    large, there are a lot filler cells to add, and the post processing, for
    example the layout extraction and LVS will be untolerably long... Since I am
    not really doing a chip, all I need is just post-layout-extraction
    transistor level simulation, so I can leave out filler cell, ...

    I don't know how to connect it manually because I don't know where does that
    wire connect to... Also that loses flexibility.

    Can experts in this group give me some help?

    Thanks a lot,

    walala, Oct 7, 2003
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