Free Seminar on SystemVerilog, Bangalore Jan 5th

Free Seminar on SystemVerilog, Bangalore, Jan 5th
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IEEE 1800, SystemVerilog is a major extension to Verilog-2001, adding
significant new features to Verilog for verification, design and
synthesis. Enhancements range from simple enhancements to existing
constructs, addition of new language constructs to the inclusion of a
complete Object-Oriented paradigm features. There are also
considerable improvements in the usability of Verilog for RTL design.
In this seminar we will walk you through the major features and the
ecosystem around SystemVerilog.

To attend this seminar, confirm your registration by sending an email
to with subject as SV Seminar. Please include
the following details in your email.
Name:
Company Name:
Official Email ID:
Contact Number:

Registration is open for our Verification using SystemVerilog public
class to be held soon (tentatively mid Jan 2008).
Venue: CVC Office (Ground Floor) (www.noveldv.com/index.php?
option=com_contact&Itemid=3)
Date: 5th Jan 2008 at 10.00 A.M
Agenda: 45 minutes presentation on SystemVerilog
15 minutes Q&A

Trainer Profile
Ajeetha Kumari, Design Verification Consultant
* Has 8+ years of experience in Verification
* Co-authored leading books in the Verification domain.
* Presented papers, tutorials in various conferences, publications and
avenues.
* Worked with all leading edge simulators and formal verification
(Model Checking) tools.
* Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV
and OOP for Verification
* Holds M.S.E.E. from prestigious IIT, Madras.