Few questions about power analysis in encounter

Hello everybody,

I am trying to do gate sizing on the synthesized
netlist from build gates. I am using a 90nm TSMC library for this. I
needed to do a transient power estimation for the original synthesized
netlist and my gate-sized netlist. I have some quick questions about
the flow and encounter in general.

1. Currently for transient power analysis I am
dumping sdf file in encounter, backannotating the sdf in verilog and
simulate and then do power analysis in encounter using the vcd file
generated. Is there any other flow I could use? I am worried the
router may place the original synthesized netlist and my sized netlist
in the different ways (thus causing different interconnect power) and
thus nullify my optimization by sizing.

2. I am using some SoCE scripts from deepchip for
this flow. I found that with default core utilization of 0.5 in
floorplanning the router is failing. I tried to increase the area of
the core by changing it to 0.025, but still >1000 DRC violations exist
in verifygeometry. I am wondering if this is this the correct way of
increasing area of my chip? Can I avoid floorplanning altogether and
let encounter decide the area of the chip by itself ? All I want, is
just a valid layout which passes verifygeometry and verifyconnectivity
and I can do RCextract for storing the spef and the sdf for subsequent
power analysis.

3. Finally, a question on the 90nm libraries. I
found that 90nm libraries uses just 4 metal layers, whereas 180nm uses
6 metal layers. But isnt it the case that subsequent technology
generations provide more metal layers...why this discrepancy? I found
180nm library provides very few or no options for sizes of cells, and
so I had to use the 90nm which supports various sizes for each library
cell.

I would really appreciate any comments or
suggestions on these. Eagerly awaiting a response.

Thanks,
Koustav