Error while netlistin when adding pins in VerilogA

Discussion in 'Cadence' started by Fritz Lange, Apr 21, 2004.

  1. Fritz Lange

    Fritz Lange Guest

    Hello,

    I have the following problem, using VerilogA.

    When I add a pin in a VerilogA module, I update my symbol cellview using
    Desing->Create Cellview-> from Cellview.
    After that I can use modify or recreate.

    In both cases I get the following error while netlisting under spectre.

    ERROR: Netlister : terminal 'vout2' of instance 'I0', in cell
    'JITTERGEN_SIM_pA1', view 'schematic' : cannot be found in the switched
    master of the instance.


    Does anybody have a solution?


    Thanks for any suggestion

    Norman
     
    Fritz Lange, Apr 21, 2004
    #1
  2. Fritz Lange

    westlaker Guest

    Why the view is schematic? Do you have a schematic view for this cell? If
    you set the view to be use (I assume you want to use VerilogA view) right,
    the netlister should not go looking for a schematic view. The way you set
    this depends on your software usage. If you are using AMS designer, it's
    through the hierachy editor.

    Hope this helps.
     
    westlaker, Apr 21, 2004
    #2
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