Error (OSSHNL-116) cadence netlist

Discussion in 'Cadence' started by shaik zubair, Jan 24, 2012.

  1. shaik zubair

    shaik zubair Guest

    Hello,

    Iam trying to design and simulate cmos Op-amp.

    I have done DRC,LVS and QRC without any error here is a
    screenshot:

    DRC:

    http://i44.tinypic.com/2428jkk.png

    Note: there are some warnings however my professor asked us to
    ignore these errors.

    LVS:

    Image - TinyPic - Free Image Hosting, Photo Sharing & Video
    Hosting

    and

    Image - TinyPic - Free Image Hosting, Photo Sharing & Video
    Hosting

    QRC:

    Image - TinyPic - Free Image Hosting, Photo Sharing & Video
    Hosting

    Schematic

    Image - TinyPic - Free Image Hosting, Photo Sharing & Video
    Hosting

    and

    Image - TinyPic - Free Image Hosting, Photo Sharing & Video
    Hosting

    When i try to generate Netlist I am getting these errors

    There is no avD24_1 in my schematic.

    ERROR (OSSHNL-116): Unable to descend into any of the views
    defined in
    the view list, 'spectre av_extracted', for the
    instance 'avD24_1' in cell 'op-amp'. Either add one of these views
    to
    the library 'PRIMLIB',
    cell 'nfetdiode' or modify the view list to contain an existing
    view.

    End netlisting Jan 24 15:11:01 2012

    ERROR (OSSHNL-514): Netlisting failed due to errors reported
    before.
    Netlist may be corrupt or may not be produced at all. Fix reported
    errors and netlist again.
    ...unsuccessful.

    Is that a problem with the schematic or layout that I need to
    modify.

    Regards

    Zubair.
     
    shaik zubair, Jan 24, 2012
    #1
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