Hello I'd like to implement differential logic gates in a TLF-library. Differential logic gates has the property, that all inputs and the output are supplementary complemented. This means, that e.g. a NAND has as inputs: A, AN, B, BN; as outputs: Q, QN. Additionally these gates needs a clock signal. The advantage of these gates is, that they produce also a inverted output, that means, that a NAND is concurrently also a AND, if the inverted output QN is used. As consequence, inverters are superfluous. My implementation of these gates in a TLF format looks like: [...] CELL(myNAND [...] PIN(Q PINTYPE(OUTPUT) //FUNCTION( CLK & (A ^ AN) & (B ^ BN) & ~(A & B) ) FUNCTION( ~(A & B) ) Load_Limit(0.16) ) PIN(QN PINTYPE(OUTPUT) //FUNCTION( CLK & (A ^ AN) & (B ^ BN) & (A & B) ) FUNCTION( (A & B) ) Load_Limit(0.16) ) [...] (I also insert a INV in this library to alleviate synthesis for now) When I try to synthesize a VHDL design, then I get for both implemented FUNCTION-solutions the errormessage: ERROR: AND not realizable in library 'my_diff_logic'. Possible cause is that the TLF does not contain an AND gate <TM-301>. It seams, that cadence is not able to handle such cases. I'm right? How can I manage this problem? Thank you for your help Egon Valentini
