Chip Assembly and Pad Assembly in ICC???

Discussion in 'Cadence' started by Lee, Aug 9, 2004.

  1. Lee

    Lee Guest

    Dear all,

    How to do verification after chip/pad assembly?Using circuit level
    simulation for a big design is slow.

    In Silicon Ensemble, I generated the clock tree for each block. After
    chip/pad assembly, the design including all blocks is much bigger. How
    can I deal with the global clock tree issue for whole design?

    Thanks,
     
    Lee, Aug 9, 2004
    #1
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  2. Lee

    Debbie Unger Guest

    UltraSim
     
    Debbie Unger, Aug 27, 2004
    #2
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