cheking if memory array is DRC correct

Discussion in 'Cadence' started by nour, Sep 11, 2008.

  1. nour

    nour Guest

    hi evevrybody! I'm writing a program that built memory arrays, and i
    want to check by a skill function that each one of them is DRC
    correct. Please can anyone help me!

    I'm using calibre DRC
     
    nour, Sep 11, 2008
    #1
  2. nour

    S. Badel Guest

    Hi... if you're not reading the answers, why would someone even answer ?
     
    S. Badel, Sep 11, 2008
    #2
  3. nour

    S.Badel Guest

    Mind me... Ok here's some clues to run calibre DRC from SKILL.

    First you need to export the layout to GDS. Set the streamOutKeys
    accordingly, then write the template file
    template=outfile("pipo.template")
    fprintf(template "streamOutKeys='%L\n" streamOutKeys)
    close(template)
    Finally run pipo
    ipcId=ipcBeginProcess(strcat("pipo strmout " fileName))
    ipcWait(ipcId)
    If you're with IC6+ the translator is xstream, the approach is the
    same.

    Next run calibre. You need to write a rules file such as
    LAYOUT PATH "drc.gds"
    LAYOUT PRIMARY "top_cell"
    LAYOUT SYSTEM GDSII
    DRC RESULTS DATABASE "drc.drc.results" ASCII
    DRC SUMMARY REPORT "drc.summary" REPLACE HIER
    INCLUDE "pdk_rules_files"
    Run calibre with ipcBeginProcess also
    ipcId=ipcBeginProcess("calibre -drc rules_files"))
    ipcWait(ipcId)

    Finally inspect the results for the errors.
     
    S.Badel, Sep 11, 2008
    #3
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