Cell libraries and place and route

Hi,

we are creating our own cell library and have a couple of questions
regarding place and route. We know that in order to be able to do place
and route we need a LEF file describing the technology/cell library,right?
We're using a 0.13 um technology and are unable to find a LEF file for
that technology. Are we supposed to create one ourselves in order to make
our cell library work with place and route tools? Should a LEF file be
distributed with our cell library?


We also wonder what files are required to be distributed with the library
to make it complete (like timing files etc.).

Thanks alot!

/Torgny Johansson & Emil Jansson

 

Yes a LEF file describing the metals and vias in addition to a lef
describing your cell libraries should be distributed with your cell
library.

At the least you should have a verilog library describing all the cell
behaviours with delay slots for simulation, .lib timing library files
for synthesis, extraction libraries for extraction tools or gds files
for extraction tools to use, gds libraries to be merged after SE flow,
spice files for transistor level lvs. There can be many other views
but these files would be good start for a basic flow.

 

With abstract generator you can create a LEF file from a cadence
technology library. most probably the tech.lib doesn't contain
all of the needed data but might be a good starting point.
use export->lef and choose technology data.

cheers,
stéphane

 

Thanks, one more question though...

Any pointers to where we can find more info about this? We're trying to
create our LEF file but we need a LEF file from the technology library to
start off with, right?
However, the technology we're using doesn't seem to provide this, atleast
we can't find it. Alternatively we could use a .dpux file (or so we've
read) but we can't find that either. Don't we need this in order to create
our LEF file or is there some other way to do it? So what do we need to
know (or have) in order to create our LEF file in the abstract generator?

Regards,
Torgny Johansson & Emil Jansson

 

DPUX is the old format used by previous version of abstract generator.
nowadays it takes technology information directly from the dfII
libraries, at the very least from ic 5.032 on but earlier already i guess.
LEF file do not have to be provided with design kits as it is a
place&route resource, you'll get one with a std cell library for example.

there are a few documents available through cdsdoc and/or sourcelink :
- LEF/DEF Language Reference
- Design Data Translator's Reference (chapter 7 - translating LEF and
DEF files)
- Abstract Generator User Guide (contains a chapter on library design
guideline, though not related to LEF)

Also, on http://crete.cadence.com you can have access to sample standard
cell libraries in which you should find a LEF file to serve as example.

cheers,
stéphane

 

Also, on http://crete.cadence.com you can have access to sample standard

The "Crete" web site *does* contain complete standard-cell libraries,
containing both ASCII TECHNOLOGY LEF & ASCII MACRO LEF (one for each
standard cell in the standard-cell library) ...

HOWEVER ... bear in mind the PURPOSE of the designs, design kits, and
documented flows supplied on crete.cadence.com are restricted for
educational use only (I think).

(I'm not a lawyer so I merely point this out.)

Please read the download agreement *before* you obtain the complete
reference libraries, complete reference designs, and complete
reference documentation.

Having said that ... our flow team created some of the components in
the generic Cadence complete design kit (CDK180, CDK090, etc.). We
created both the 90nm technology LEF and the macro LEF (one for each
of the hundreds of standard cells in the 90nm standard-cell library)
using Cadence software. We also used the services of Prolific &
Circuit Semantics to characterize the 90nm cells i.e., LIBERTY & TLF
.... (student slave labor characterized the 180nm cells).

The 180nm crete reference designs (e.g., the Eaglet RF, analog,
mixed-signal, memory, I/O, digital, etc. cell-operated garage door
opener chip), have been used by over a thousand university students to
date in their various classwork.

Back on the topic of LEF creation, if you have the standard-cell
schematics and layout, you *can* create the macro & library LEF
yourself (using the Cadence abstract generator directly from the DFII
database), so, you *can* do it yourself ...

However, normally, you'd get BOTH technology LEF and macro LEF when
you picked up the industry standard standard-cell library.

My suggestion is to FIRST talk to your standard-cell library vendor.
They *must* have these items for most (older) flows to work.

Nowadays, with OpenAccess 2.2, we see tremendously less of a need for
these formats, but, that's a whole 'nother discussion.

John Gianni

 

Thanks for the tips, we have alot to learn it seems...

Regards
Torgny Johansson
Emil Jansson

 

Ok, we've made so far as to finding the required files and stuff and now
we've run into new problems when actually creating the abstract in
abstract generator. After some effort we managed to get the tool to
recognize the pins in our design but now when we try to create the
absstract it fails with the following message:

WARNING (ABS-1076): Cell inverter: Terminal a_bar has no pins on
Metal1-Metal2 Routing grid
WARNING (ABS-1076): Cell inverter: Terminal a has no pins on
Metal1-Metal2 Routing grid

We suppose that this has something to do with the terminals/pins not being
positioned right in the layout.
metal1's pitch is 1.3 and it's offset is 0, metal2's are 1.4 and 0.7
respectively. So we placed the pins at multiples of the pitch values
however that doesn't seem to do it (or we've done it wrong).

Anybody recognize this problem or have any tips on what to do?

Thanks!

Regards
Torgny Johansson