Capacitor Layout in 0.18 um in Cadence

Discussion in 'Cadence' started by Karim, Jul 24, 2003.

  1. Karim

    Karim Guest

    How? What layers do i use? I believe i only have only 1 poly layer.

    Thanks

    Karim
     
    Karim, Jul 24, 2003
    #1
  2. Karim

    Vikas Vijay Guest

    hello karim,
    i don't know about 0.18um tech in particular but normally the
    following structures will be extracted as caps if Extract_caps switch
    is on.

    ``metal1''/``poly'' overlap enclosed by ``cap_id''

    ``metal2''/``metal1'' overlap enclosed by ``cap_id''

    ``metal3''/``metal2'' overlap enclosed by ``cap_id''

    ``metal4''/``metal3'' overlap enclosed by ``cap_id''

    ``metal5''/``metal4'' overlap enclosed by ``cap_id''

    ``metalcap''/``metal5'' overlap

    ``poly''/``active'' overlap enclosed by ``cwell'' (thin-oxide
    capacitor)

    ``poly''/``polycap'' overlap

    as given at
    http://www.cerc.utexas.edu/~chp/ncsu/local/doc/cdsmgr/diva_verification.html#extraction

    Anyone with more info on this please reply. i am also interested in
    0.18u tech in particular.

    -vikas
     
    Vikas Vijay, Jul 25, 2003
    #2
  3. Karim

    Andrew Beckett Guest

    These things are all technology dependent. What you are saying depends on which
    0.18u technology you are using - the layers will be different from TSMC, UMC
    Chartered, IBM, etc,etc.

    If you are using a particular technology, there will be electrical rules which
    define this kind of information...

    Andrew.
     
    Andrew Beckett, Jul 28, 2003
    #3
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