Can I do LVS between gate netlist and transistor netlist in Diva?Thanks

Hi,

In my schematic view, I use gate level netlist. In my layout view, if
I flatten the design, the extracted view will be transistor level
netlist. Can I do LVS for the gate level netlist and the transistor
level netlist in Diva? In the Cadence manual, it said that LVS should
be done in the same level. I am not quite sure about this.

One more question. Can I get the gate level netlist from layout view?

I also feel confused. In the layout view of my design, if I don't
flatten the design, diva DRC (flat method or hierachy method, full
check) of the layout has errors such as "INFO:hot well" "minimum NDIFF
to NTUB spacing = 2.6". But If I do flatten the design, diva DRC (flat
method and full check) of the layout has no errors. Why? Can this
problem be fixed?

Thanks,

 

You cannot run LVS without both netlists being at the same level of
detail. You handle this by having transistor level schematic views of
the gates. This is the normal case in PDK libraries.

It is difficult to say what is happening with your DRC. If full, flat
DRC does not give you an error, then it should be considered to be
correct. Hierarchical DRC is not designed to be 100% correct. It is a
way to quickly find and fix errors in a design that is larger than Diva
can handle quickly. Simply ignore any hierarchical mode errors that do
not make sense.