can I allocate more memory to icfb extraction operation?

Dear all,

I am extracting "extract view" from my "layout view"... The 10000 cell
design is not very large, but I wait for hours and hours the extraction
operation seems no ending...

Can anybody tell me how to increase the memory allocated to icfb
"extraction" operation that it might speed my operation?

Thanks a lo,t

-Walalla

 

If you're doing this with Diva, then that's potentially quite large... (depends
how big the cells are, and if you're doing it flat, and if you're extracting
parasitics as well).

There's no way to control the amount of memory allocated to any executable
because it is all dynamic - the tools ask for memory that they need (up to what
is available from the system, and up to the maximum for a 32 bit executable (or
64 bit if you're using that)).

It may be that you don't have enough physical RAM; the tools may be getting
enough Virtual Memory, but if there's not enough actual RAM on the machine,
it may be thrashing as it swaps VM chunks back and forth to disk. For
a simple way of viewing this, the utility "top" can be used.

Andrew.

 

Generally speaking, Diva is designed to use little memory. The most
memory consuming operation is the geomConnect rule. There is no way to
increase the amount of memory it will use.

A 10,000 cell design seems quite large. I'm assuming you are talking
about standard cells with an average of 6 transistors per cell. Most
experienced users of Diva find that to be about the limit in design size
for Diva. If you are also doing parasitic resistance and capacitance, it
takes even longer.

Instead of asking how to solve what you think is the problem, we can
help you better if you tell us what is going on. Something like "my
parasitic extraction run seems to be spending all it's time executing
the geomConnect rule" would tell us a great deal. We would ask if you
have large vias farms. Then tell you to merge them since they tend to
make resistance extraction run forever.

It is also quite possible that you have simply exceeded the capacity of
the tool. Cadence has always said it is intended as a cell, block and
small design verification tool. There is a reason Cadence has always
sold Dracula and Assura for full chip verification.