Cadence Virtuoso DRC check error

We are UG students, presenly working with Cadence Virtuoso. After
creating a simple layout of an inverter, these are a few of the errors
which appeared in the log file when we tried running Assura DRC check
using NCSU_TechLib_ami06/divaDRC.rul.

error: Illegal input layer 'geomGetEdge(geomAndNot(elec
geomButting(elec elecHighres)))' found in drc().
error: Illegal input layer 'active' found in geomAnd().
error: Undefined layer - elecHighresEdge.
Errors exist in the rules file
'/home/chiptapeout/cadence/ncsu-cdk-1.5.1/lib/NCSU_TechLib_ami06/
divaDRC.rul'.
*WARNING* Failed to build VDB. Cannot submit DRC Run.
Assura DRC: State loaded "Last"

Could anyone please help us out?

 

I am not any sort of an expert on Assura, but it seems like you are
using the Assura product, but Diva DRC rules.

I think Cadence has several "DRC" checking tools, Diva (the older
one), Assura (a newer one), and there are others. The files that
actually contain the rules themselves: divaDRC.rul (from your error
message)...are meant for one tool or the other. I don't know if they
are compatible with one another. There may be a way to convert diva
DRC rules files to be readable by Assura, but I don't know how to do
that.

Perhaps others can comment on this.

Have you tried just using Diva DRC checker, instead of the Assura DRC
checker with your divaDRC.rul file? Maybe that will help.

Good luck.

 

We had asked NCSU Help desk too, they assured us that Diva rules work
fine with Assura. So this is some other problem. Can someone with a
working DivaDRC rules file of NCSU_ami_06 technology share the
package?
Has anyone faced a similar problem? And if yes, how did they rectify
it?