Cadence layout design - Extraction error

Discussion in 'Cadence' started by Nilani Ratnasri, Mar 2, 2023.

  1. Nilani Ratnasri

    Nilani Ratnasri

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    Hello,
    I am using the cadence virtuoso IC617 version and SMIC_018_MMRF_oa library file. When designing the layout of the inverter design, I used the calibre method to run DRC and LVS. Therefore I didn't get any error messages. when I clicked run PEX, the PEX transcript showed a Fatal error: rules files must contain a capacitance order statement. And extraction of the inverter has not happened. Could you tell me how to resolve this error?
     
    Nilani Ratnasri, Mar 2, 2023
    #1
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